Doubly-Robust-Estimation-V2 Machine Learning
Doubly Robust Estimation (Extended Study) Introduction & Motivation Doubly Robust Estimation (Extended Study) addresses a central problem in estimating causal effects…
1,686 technical terms and definitions
Doubly Robust Estimation (Extended Study) Introduction & Motivation Doubly Robust Estimation (Extended Study) addresses a central problem in estimating causal effects…
Doubly Robust Estimation (Extended Study) Introduction & Motivation Doubly Robust Estimation (Extended Study) addresses a central problem in estimating causal effects…
Doubly Robust Estimation (Extended Study) Introduction & Motivation Doubly Robust Estimation (Extended Study) addresses a central problem in estimating causal effects…
recommendation systems
Doubly Robust Rec is off-policy estimation combining direct outcome models with propensity correction for robustness. - It reduces bias if either the reward model or propensity…
cmp down force, polishing pressure, cmp contact pressure, preston equation, preston law, removal rate cmp, multi zone carrier, cmp
CMP removal rate is the thickness or mass of target thin-film material polished from a semiconductor wafer per unit time during chemical mechanical planarization, traditionally…
class imbalance, undersampling
Down-sampling is reducing the frequency of overrepresented classes or domains to improve training balance - It limits dominance from high-volume sources that would otherwise crowd…
downstream asher strip rate uniformity prediction machine learning, downstream asher, strip rate uniformity, downstream asher strip rate uniformity prediction
Downstream Asher Strip Rate Uniformity Prediction with Machine Learning Introduction & Motivation Downstream Asher Strip Rate Uniformity Prediction with Machine Learning addresses…
downstream plasma asher chamber wall deposit prediction machine learning, downstream plasma, asher chamber wall, downstream plasma asher, plasma asher chamber
Downstream Plasma Asher Chamber Wall Deposit Prediction with Machine Learning Introduction & Motivation Downstream Plasma Asher Chamber Wall Deposit Prediction with Machine…
transfer learning
Downstream Task is the target task that a pre-trained model is applied to after self-supervised or supervised pre-training — used to evaluate the quality of learned…
production
Downtime is time when a tool is not available for production due to failures, maintenance, or other issues, directly impacting fab capacity and output. Downtime categories: (1)…
production
Downtime analysis is the structured investigation of tool stoppage events to quantify loss drivers and identify highest-return corrective actions - it converts raw outage logs…
dp-sgd, training techniques
DP-SGD is differentially private stochastic gradient descent that clips per-example gradients and adds calibrated noise - It is a core method in modern semiconductor AI serving…
dp-sgd, differentially private sgd, privacy
DP-SGD (Differentially Private Stochastic Gradient Descent) is the foundational algorithm for training machine learning models with formal differential privacy guarantees…
diffusion sampler, stable diffusion
DPM++ (Diffusion Probabilistic Model++) is an advanced sampling method for diffusion models — generating high-quality images in fewer steps than DDPM through improved ODE solvers…
generative models
DPM-Solver is a family of high-order ODE solvers specifically designed for the probability flow ODE of diffusion models, providing faster and more accurate sampling than generic…
generative models
DPM-Solver is the family of high-order numerical solvers for diffusion ODEs that attains strong quality with very few model evaluations - it is one of the most effective…
defects per million, quality metric
DPMO (Defects Per Million Opportunities) is the universal, normalized quality metric used across the global semiconductor, automotive, aerospace, and manufacturing industries…
dpmo, quality & reliability
DPMO is defects per million opportunities, a normalized metric expressing defect frequency relative to total opportunities - It enables cross-process comparison of quality…
direct preference, simpler
Direct Preference Optimization (DPO) is the fine-tuning algorithm that aligns language models with human preferences without requiring a separate reward model or reinforcement…
dpp, recommendation systems
DPP Rec is determinantal point process based recommendation for diversity-aware subset selection. - It models item-set probability so high-quality but mutually dissimilar items…
dppm, quality
DPPM (Defective Parts Per Million) is the primary quality metric measuring the rate of defective devices shipped to customers — calculated as , representing the outgoing quality…
dppm, yield enhancement
DPPM is defective parts per million, a quality metric that quantifies escaped defect rate in shipped units - DPPM normalizes field or outgoing defects by shipped volume to track…
dprnn, audio & speech
DPRNN is dual-path recurrent neural network tailored for efficient long-sequence speech separation - It applies stacked dual-path recurrent blocks to scale temporal modeling…
smartnic, smart nic, data processing unit, infrastructure offload, dpu infrastructure offload chip, nvidia bluefield 3 dpu, amd pensando, nvme over fabrics
A DPU, or data processing unit, also sold as a SmartNIC, is the third class of processor in a modern datacenter, sitting alongside the CPU and the GPU. Where the CPU runs…
dqn, reinforcement learning
DQN (Deep Q-Network) is the foundational deep reinforcement learning algorithm that combines Q-learning with deep neural networks — using a CNN to estimate the action-value…
DRAEM Discriminative Reconstruction Embedding for Defects Introduction & Motivation DRAEM Discriminative Reconstruction Embedding for Defects addresses a central problem…
optimization
Draft Model is the fast proposal model used in speculative decoding to generate candidate tokens - It is a core method in modern semiconductor AI serving…
inference
Draft model selection is the process of choosing the proposer model used in speculative decoding to maximize acceptance rate and net speedup under quality constraints - selection…
dragonfly algorithm navigation, dragonfly algorithm, algorithm navigation
Dragonfly Algorithm Navigation Introduction & Motivation Dragonfly Algorithm Navigation addresses a central problem in ml process control and path-quality-optimization prediction…
Dragonnet Targeted Regularization for CATE Estimation Introduction & Motivation Dragonnet Targeted Regularization for CATE Estimation addresses a central problem in causal…
drain-induced barrier lowering prediction, drain-induced barrier lowering, barrier lowering prediction, drain-induced barrier, barrier lowering, lowering prediction
Drain-Induced Barrier Lowering Prediction with Machine Learning Introduction & Motivation Drain-Induced Barrier Lowering Prediction with Machine Learning addresses a central…
drain-induced barrier lowering prediction, drain-induced barrier lowering, barrier lowering prediction, drain-induced barrier, barrier lowering, lowering prediction
Drain-Induced Barrier Lowering Prediction with Machine Learning Introduction & Motivation Drain-Induced Barrier Lowering Prediction with Machine Learning addresses a central…
ibm 1968 dennard sequential versus combinational device, 1t1c dram 1968 output depends on its own past state, dram memory 1968 first device this project built for persistence
Why Memory Needs an Entirely Different Structure Than Logic: The First Device This Project Has Built for Persistence, Not Speed 1. Why Every Earlier Series Built a Device That…
ibm dennard 1968 one transistor one capacitor memory cell, 1t1c dram charge storage replaces multi transistor latch, dram 1968 access transistor controls write and read
Store a Bit as Charge on a Capacitor, Not as a Latch of Transistors: Dennard's Radical Simplification 1. Replace a Circuit That Continuously Defends Its State with One Physical…
ibm dennard 1t1c word line bit line storage node transistor, 1t1c dram access mosfet selected row shared bit line, dram 1968 reuse silicon gate process for access transistor
Build the Access Transistor Using the Self-Aligned Gate Process Just Completed: A Direct Reuse of 1967's Silicon-Gate Process 1. The New Memory Architecture Does Not Require a New…
ibm dennard 1t1c mos capacitor stores bit charge, 1t1c dram capacitor area oxide thickness capacitance, dram 1968 mos capacitor becomes functional storage element
Build the Storage Capacitor Beside the Transistor: Turn the MOS Capacitor from a Test Structure into the Bit Itself 1. Reuse the Gate-Oxide-Silicon Stack for a Completely…
ibm dennard 1t1c subthreshold junction dielectric leakage, 1t1c dram storage node charge decay leakage current, dram 1968 dynamic memory leakage requires refresh
Confront Leakage: Why the Charge Does Not Stay Forever 1. The Same Off-State Current That Was Negligible for CMOS Logic Is Now the Central Failure Mechanism The 1963 CMOS series…
ibm dennard 1t1c write wait read retention test, 1t1c dram weakest cell retention distribution guard band, dram 1968 refresh interval protects stored charge margin
Measure the Retention Time and Set the Refresh Interval 1. Retention Time Is Measured from a Completed Write to the Last Reliable Read Step 5 established that leakage continuously…
ibm dennard 1t1c bit line charge sharing read, 1t1c dram sense amplify restore after every read, dram 1968 reading capacitor requires write back
Confront Destructive Readout: Reading the Cell Disturbs the Charge Being Read 1. The Bit Cannot Be Observed Without Connecting It to a Much Larger Electrical Node A 1T1C cell has…
ibm dennard 1t1c cell area compared with 6t memory, 1t1c dram repeated cell tile and shared periphery density, dram 1968 smaller cell enables higher bit density
Measure the Area Advantage Against a Six-Transistor Latch 1. Compare Repeated Cell Footprints, Not Transistor Counts in Isolation The density advantage of Dennard's cell comes…
ibm dennard 1t1c cell density shared array overhead, 1t1c dram refresh occupancy sensing restore tradeoff, dram 1968 qualify complete memory macro architecture
Qualify the Trade: Density Against Refresh Complexity 1. The Cell Becomes Simpler by Moving Work into the Array The 1T1C architecture does not eliminate the functions a memory…
ibm dennard 1t1c dynamic random access memory classification, 1t1c dram cell array macro release qualification, dram 1968 compact cell shared circuitry enables large memory
Classify and Release: The Architecture That Makes Large-Scale Memory Possible 1. Classify the Finished Device by What It Stores and What It Requires The completed one-transistor…
buried word line DRAM, BWL DRAM, recessed channel array transistor, RCAT DRAM, saddle-fin DRAM transistor, GIDL DRAM word line, word line GIDL, sub word line driver, hierarchical word line, DRAM Vpp word line boost
DRAM Buried Word Line: Saddle-Fin Gate Architecture, the GIDL Trade-Off, and Hierarchical Row Activation A buried word line (BWL) is a DRAM access-transistor gate that no longer…
dram capacitor aspect ratio uniformity prediction, dram capacitor aspect, capacitor aspect ratio, aspect ratio uniformity, ratio uniformity prediction, aspect ratio
DRAM Capacitor Aspect Ratio Uniformity Prediction with Machine Learning Introduction & Motivation DRAM Capacitor Aspect Ratio Uniformity Prediction with Machine Learning addresses…
dram capacitor dielectric leakage current prediction, dram capacitor dielectric, capacitor dielectric leakage, dielectric leakage current, dram capacitor
DRAM Capacitor Dielectric Leakage Current Prediction with Machine Learning Introduction & Motivation DRAM Capacitor Dielectric Leakage Current Prediction with Machine Learning…
dram capacitor leakage drift prediction, dram capacitor leakage, capacitor leakage drift, leakage drift prediction, dram capacitor, capacitor leakage, leakage drift, drift prediction
DRAM Capacitor Leakage Drift Prediction with Machine Learning Introduction & Motivation DRAM Capacitor Leakage Drift Prediction with Machine Learning addresses a central problem…
ECC DRAM, SECDED, Hamming code DRAM, Chipkill, Advanced ECC, ECC DIMM, single error correction double error detection
DRAM ECC: Hamming SECDED Architecture, Reliability Theory, and the Chipkill Application ECC is the layer that stops pretending the physics underneath it is perfect. Every…
dram cell structure, dram capacitor, dram refresh, 1t1c dram cell
DRAM (dynamic random-access memory) stores each bit as charge on a tiny capacitor, gated by a single access transistor — the '1T1C' cell. It is 'dynamic' because that charge leaks…
dram refresh bitmap repair prediction, dram refresh bitmap, refresh bitmap repair, bitmap repair prediction, dram refresh, refresh bitmap, bitmap repair, repair prediction
DRAM Refresh Bitmap Repair Prediction with Machine Learning Introduction & Motivation DRAM Refresh Bitmap Repair Prediction with Machine Learning addresses a central problem…
dram refresh command overhead prediction, dram refresh command, refresh command overhead, command overhead prediction, dram refresh, refresh command, command overhead
DRAM Refresh Command Overhead Prediction with Machine Learning Introduction & Motivation DRAM Refresh Command Overhead Prediction with Machine Learning addresses a central problem…