Analog Simulation
Analog Circuit Simulation (SPICE) is the computational method that solves the nonlinear differential equations governing transistor, resistor, capacitor, and inductor behavior to predict the time-domain, frequency-domain, and DC operating characteristics of analog circuits — the essential validation tool for amplifiers, PLLs, ADCs, power management ICs, and RF circuits where digital simulation cannot capture continuous-signal behavior. SPICE (Simulation Program with Integrated Circuit Emphasis, UC Berkeley 1973) and its commercial successors are the universal language of analog circuit design.
Core SPICE Analysis Types
| Analysis | Description | Output | Use |
|---|---|---|---|
| .DC | Sweep DC bias | I-V curves, operating point | Bias, large-signal |
| .AC | Small-signal frequency sweep | Gain, phase, bandwidth | Amplifier frequency response |
| .TRAN | Time-domain integration | Waveforms vs. time | Transient behavior, settling |
| .NOISE | Noise power spectral density | Input/output referred noise | Noise figure, SNR |
| .MONTE | Monte Carlo statistical | Distribution of outputs | Yield prediction, mismatch |
| .SENS | Sensitivity analysis | Partial derivatives | Identify critical components |
SPICE Transistor Models
- BSIM3/4: Standard for bulk CMOS, accurate for 250nm–28nm.
- BSIM-CMG: FinFET and GAA (Common Multi-Gate) model — industry standard from 14nm.
- PSP: Physics-based model with excellent symmetry at Vds=0 — used for RF and precision analog.
- EKV: Compact model popular in analog design (explicit in gm/Id).
- Model parameters extracted from silicon measurements → library from foundry PDK.
SPICE Solvers
- Newton-Raphson iteration: Linearizes nonlinear circuit equations → iterate to convergence.
- Numerical integration (TRAN): Trapezoidal or gear method → timestep control by local truncation error.
- Convergence challenges: Circuits with many nonlinearities, regenerative circuits (latches, oscillators) → can fail to converge → requires initial condition hints or modified analysis.
Commercial SPICE Tools
| Tool | Vendor | Strength |
|---|---|---|
| HSPICE | Synopsys | Most accurate, industry standard for signoff |
| Spectre | Cadence | Best-in-class Monte Carlo and RF analysis |
| Eldo | Mentor/Siemens | European analog standard |
| ngspice | Open source | Free, SPICE3 compatible, research/hobbyist |
| Xyce | Sandia Labs | Parallel SPICE for very large circuits |
Monte Carlo Simulation
- Runs SPICE N=1000–10,000 times with random process/mismatch parameters.
- Each run: VT, COX, µ randomly varied per statistical model (σ from foundry characterization).
- Output: Distribution of gain, offset, Vmin, bandwidth → estimate yield.
- Purpose: Verify 3σ or 6σ design robustness without physical wafers.
- Critical for: SRAM bit cell, current mirror mismatch, ADC linearity.
Corner Simulation
- Run .DC/.AC/.TRAN at: TT, SS, FF, SF, FS process corners × voltage extremes × temperature extremes.
- Verify: Circuit functions (gain > spec, offset < spec) at all corners.
- Typical: 5 corners × 3 voltages × 5 temperatures = 75 simulation runs per circuit.
Fast SPICE for Large Circuits
- Full SPICE: Accurate but slow — 10,000 transistors × 1 µs simulation can take hours.
- Fast SPICE (Synopsys HSIM, Cadence UltraSim): Reduced-order models, event-driven → 10–100× speedup.
- Trade-off: Slightly less accurate for exact settling and coupling effects.
- Application: Full PLL transient simulation, SRAM access time across address sweeps.
Simulation Accuracy vs. Silicon
- Target: SPICE AC gain vs. silicon within ±0.5 dB, DC offset within ±5 mV.
- Corner correlation: Simulated SS vs. measured slow silicon within ±10%.
- RO (Ring Oscillator) frequency: SPICE within ±5% of silicon → validates transistor model.
Analog SPICE simulation is the design medium through which analog circuits are conceived, refined, and proven before the first silicon is made — by solving the physics of electron flow through every transistor simultaneously, SPICE-based simulation enables analog designers to iterate designs thousands of times in software in the days it would take to design and fabricate a single test chip, compressing what once required years of hardware iteration into a design cycle of weeks.