Backside

Backside power delivery networks (BSPDN) move the power distribution grid from the front side of the wafer, where it competes with signal routing, to the back side, where it competes with nothing. The transistor layer is then contacted from both faces: signals from above through conventional BEOL, power from below through nano-scale through-silicon vias. It is the most significant change to interconnect architecture since dual damascene.

The problem it solves

In a front-side network, power travels from package bumps down through every metal level to reach the device. Each level contributes resistance, and the wide power straps on the lower levels consume routing tracks that signals need. The voltage actually reaching a cell is degraded by

\Delta V_{\text{IR}} = I_{\text{cell}} \cdot R_{\text{grid}}

and because dynamic current scales with activity while grid resistance rises as wires narrow, IR drop has been worsening every node. Backside delivery attacks $R_{\text{grid}}$ directly: the backside metal is built on a free surface, so it can be thick and wide, with sheet resistance an order of magnitude below a comparable front-side layer. The improvement is implementation-specific: Intel reports that 18A PowerVia can reduce worst-case dynamic voltage droop by as much as 10×. That is a product-level result, not a universal constant for every backside network.

Static IR drop is only half of the power-integrity problem. A switching block does not ramp its current gently. Its current edge creates an inductive notch before the package regulator can react, followed by a resistive plateau while local decoupling capacitance discharges:

\Delta V(t) \approx I(t)R_{\text{path}} + L_{\text{path}}\frac{dI}{dt}, \qquad Z_{\text{target}} = \frac{\Delta V_{\text{allow}}}{\Delta I}

Backside delivery shortens and widens the final path to the device, reducing both resistance and loop inductance. On-die and package decoupling supply the first instants of the current step; the voltage regulator restores charge later. A PDN succeeds only when the whole impedance curve stays below $Z_{\text{target}}$ across the frequency range the workload excites.

This is the commercial toll bridge: backside metal by itself is not the product. The defensible capability is co-optimising the process stack, standard-cell library, extraction models, decap placement and package regulator so sign-off predicts both DC IR drop and nanosecond droop. A customer cannot recover that integration merely by drawing wider rails late in physical design.

Buried power rails

The enabling front-side change is the buried power rail. Instead of running $V_{DD}$ and $V_{SS}$ as M0/M1 wires above the fins, the rail is sunk into a trench in the shallow-trench isolation, below the device layer, filled with a refractory metal — typically tungsten or ruthenium, chosen because they survive the full thermal budget that follows. The rail is then contacted from beneath by a nano-TSV.

Removing the rails from the cell's metal stack is what unlocks track-height scaling. A standard cell's width is quantised in routing tracks, and two of them were historically spent on power:

T_{\text{cell}} = T_{\text{signal}} + T_{\text{power}} \;\longrightarrow\; T_{\text{cell}} \le 5T

Moving power below takes the cell from 6T toward 5T and below, a direct area reduction of roughly 15 to 20 percent that costs nothing in transistor performance.

Nano-TSV and the back-to-front contact

The via that joins the two faces is not a classical package-level TSV. Its geometry is integration-specific: demonstrated backside contacts range from narrow, high-aspect-ratio structures to short vias through only a few hundred nanometres of remaining silicon. The hard requirement is landing on a buried rail or power tap only tens of nanometres wide while keeping resistance and overlay error inside budget. The process sequence is bonding to a carrier, grinding and etching the device wafer down to a few hundred nanometres with a buried etch-stop layer, then patterning and filling the vias from beneath.

Two parameters dominate the electrical result. The via resistance itself scales as

R_{\text{nTSV}} = \frac{\rho\, L}{A} = \frac{4\rho\, L}{\pi d^{2}}

so halving the diameter quadruples resistance, and the drive to shrink the via for density fights the drive to widen it for conduction. Alongside it sits the back-to-front contact resistance at the nano-TSV to rail interface, governed by the specific contact resistivity $\rho_c$ over a contact area that is by construction tiny:

R_{c} = \frac{\rho_c}{A_{c}}

This interface, not the via body, is usually the limiting resistance in a BSPDN, and it is why low-temperature silicide and barrier metallurgy on the backside are active process-development areas.

The thermal penalty

The gain is not free. Thinning the silicon reduces lateral heat spreading and can intensify local hotspots, while a sufficiently thick backside metal stack can conduct and spread heat. The net junction-to-case result therefore depends on silicon thickness, metal geometry, bonding interfaces and the cooling boundary condition; it is not automatically worse or better:

\theta_{jc} = \frac{T_j - T_c}{P}, \qquad \theta_{jc}^{\text{BSPDN}} = f(t_{Si},\, t_{metal},\, interfaces,\, cooling)

The device layer ends up thermally sandwiched, and the self-heating that the improved IR drop was meant to relieve partly returns as a temperature rise. Because carrier mobility degrades and leakage climbs with temperature, and because electromigration lifetime carries an Arrhenius term, the thermal penalty must be budgeted explicitly rather than treated as a second-order effect. Practical designs recover margin through thicker backside metal, deliberate thermal vias, and placement that spreads high-activity blocks.

Parameter	Front-side PDN	Backside PDN
Grid resistance	baseline	5–10× lower
Cell track height	6T and above	5T and below
Routing congestion	power competes with signal	signal owns the BEOL
Thermal path	thick-silicon baseline	design-dependent: less silicon spreading, more backside-metal spreading
Process complexity	mature	wafer bonding, thinning, backside litho

HBM4's power delivery network is a different problem wearing the same equation. Everything above describes power moving *down* into one logic die's transistor layer. An HBM4 stack instead has to move power *up*, from the package through the base die and then through every one of 12 to 16 DRAM dies stacked above it, and the same $\Delta V_{\text{IR}} = I \cdot R_{\text{grid}}$ now accumulates in series, one die's worth of power TSVs at a time.

Stack height turns that single-level $R_{\text{grid}}$ into a series chain: the voltage a top die actually receives has already been degraded by every power TSV and every die-to-die bond beneath it.

\Delta V_{\text{stack}} \approx I \sum_{k=1}^{N} R_{\text{nTSV},k}

The base die's on-die regulation — the same PMIC function this project's base-die article already placed there — exists precisely to intercept that accumulating drop as close to the dies as possible, rather than asking a single package-level regulator far away to hold every die in a 16-high stack to the same tight tolerance.

That is also why HBM4's power problem can never be solved by the base die alone. Local regulation buys headroom, but every additional watt the 2048-bit interface and any on-die compute now draws still has to cross the same series of nano-TSVs, and the same keep-out-zone tax from this project's TSV density article still applies to every power via exactly as it does to every signal via.

Where it stands

Commercial adoption is now concrete but not uniform across every “2 nm” process. Intel 18A with PowerVia entered production in 2025. TSMC N2 began without a backside rail, while A16 with Super Power Rail is scheduled for volume production in the second half of 2026. BSPDN is therefore a foundry- and process-specific scaling choice, not a feature implied by the node label. The remaining challenge is simultaneous closure of voltage, heat, yield and cost.

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