Backside Contact Formation
Backside contact formation is the process of landing an electrical contact on the underside of a transistor after the wafer has been flipped and thinned. It is the step that makes backside power delivery real: without a low-resistance path from the backside metal to the source/drain or buried rail, moving the power network behind the wafer achieves nothing.
The resistance that matters
A metal-to-silicon contact is a Schottky junction, and current crosses it by thermionic emission over the barrier or by tunnelling through it. The specific contact resistivity depends exponentially on barrier height and doping:
Two levers follow directly. Lowering the barrier height $\phi_B$ by choosing the right silicide helps linearly in the exponent; raising the doping $N_D$ helps as $1/\sqrt{N_D}$ and is the stronger lever in practice, which is why degenerate doping of the contact region is universal. The contact resistance seen by the device is then
and because $A_c$ on a backside contact is set by the footprint of a single device, it is brutally small. Contact resistivity targets below $10^{-9}\ \Omega\!\cdot\!\text{cm}^{2}$ are required, and the contact is routinely the dominant parasitic in the path.
The low-temperature constraint
Front-side contacts are formed early and can be annealed aggressively. A backside contact cannot. By the time the wafer is flipped and thinned, the full BEOL stack exists on the other side: copper interconnect, low-k dielectric, and in advanced flows bonded interfaces. Copper agglomerates and low-k degrades well below the temperatures classical silicidation prefers, so the entire backside module is capped near 400 °C and often lower.
There is no universal backside silicide. NiPtSi is an established low-temperature option: platinum delays agglomeration and the unwanted NiSi₂ transition, at the cost of a more complex metal and etch. Current research also demonstrates self-limited ultrathin Ti silicide near 350 °C and nanosecond-laser silicidation that localises heating while keeping the existing Cu/low-k stack below 400 °C. The winning stack depends on contact polarity, junction damage, film continuity and the thermal history that the completed front side can tolerate.
Barrier metallurgy
Between silicide and fill metal sits a barrier, and on the backside its job is unusually hard. It must block metal diffusion into silicon that already contains finished devices, adhere to both surfaces, survive the thermal excursions that follow, and do all of this while occupying almost none of the contact's cross-section — every nanometre of barrier is a nanometre not carrying current.
Titanium nitride deposited by ALD remains the default, because ALD gives conformality in a high-aspect-ratio via that sputtering cannot. The fill is tungsten or, increasingly, ruthenium and molybdenum: as discussed under resistivity scaling, the figure of merit in a sub-20 nm via is the $\rho_0 \lambda_{\text{mfp}}$ product rather than bulk resistivity, and copper's long mean free path makes it a poor choice at these dimensions even before the barrier displacement penalty is counted.
| Silicide | Formation T | Resistivity | Note |
|---|---|---|---|
| NiSi | 400–500 °C | 14–20 µΩ·cm | low budget, transforms to NiSi₂ |
| NiPtSi | 400–500 °C | 15–22 µΩ·cm | Pt stabilises phase and morphology |
| CoSi₂ | 700–900 °C | 15–20 µΩ·cm | too hot for backside |
| Ti silicide | conventional furnace: high; ultrathin laser process demonstrated near 350 °C | process-dependent | localized anneal is a backside-development path |
Alignment to the front side
The contact must land on a feature patterned from the opposite face of the wafer, through a few hundred nanometres of remaining silicon. Overlay is therefore referenced to buried alignment marks read through the substrate, and the accuracy achievable there — not the lithographic resolution — sets how small the contact can be. A misregistered backside contact either misses its target entirely or shorts to an adjacent node, so overlay budget is spent here more carefully than almost anywhere else in the flow.
Overlay becomes electrical yield. If the buried landing feature has width $W$, the contact has diameter $d$, and the required electrical enclosure is $e$, the one-sided placement margin is
The second condition is a manufacturability rule rather than a geometric ideal: mean registration error $Delta x$ and three standard deviations of overlay variation must fit inside the enclosure margin. A contact can remain electrically connected while losing enough overlap area to raise $R_c$, so resistance fails continuously before the binary open-circuit limit.
This is why extreme thinning and overlay metrology are part of the contact module, not separate support steps. Thinner residual silicon improves the visibility and fidelity of buried alignment marks and shortens the contact, but it also tightens thickness-uniformity and mechanical-control requirements across the wafer. The process window is jointly owned by thinning, lithography, etch and contact resistance.