Bicmos Process Flow

BiCMOS Process Integration is simultaneous fabrication of bipolar (NPN/PNP) and CMOS transistors on the same chip for high-speed analog/RF applications combining bipolar gain and CMOS integration density.

Bipolar Transistor in BiCMOS:
- NPN: vertical transistor, base-emitter junction and collector formed
- Gain: current gain (β) ~100-1000 typical (vs CMOS gate voltage dependency)
- Frequency: cutoff frequency fT achievable >300 GHz at 130nm technology
- SiGe HBT: heterojunction bipolar transistor using Ge in base for enhanced fT
- Power dissipation: bipolar bias current higher than CMOS (power vs speed tradeoff)

Process Complexity:
- Mask count: 14-20 masks for BiCMOS vs 10-12 for CMOS only
- Collector sinker: deep implant/dopant drive to reduce collector resistance
- Deep trench isolation: enhanced isolation between bipolar and CMOS regions
- Additional processing: base/emitter/collector implants and anneal cycles
- Thermal budget: bipolar anneal cycles must avoid disrupting CMOS transistor profiles

BiCMOS Performance Advantages:
- High-speed I/O: output drivers with bipolar output stage (stronger pull-up/down)
- Transimpedance amplifier (TIA): bipolar input stage (lower input impedance, lower noise)
- Voltage reference: bandgap reference circuit (bipolar-only function)
- Oscillator: bipolar oscillator core (lower phase noise vs CMOS)

SiGe Technology Evolution:
- Base engineered with Ge: Ge concentration ~10-20% in base
- Band gap narrowing: lower turn-on voltage, higher gain
- fT increase: >300 GHz at 130nm BiCMOS generation
- Transition frequency vs frequency improvement: enables higher operating frequencies

Applications:
- High-speed wireline (100GbE transceiver): TIA + limiting amplifier + CDR (clock and data recovery)
- mmWave RF (77 GHz radar): oscillator + power amplifier + LNA
- Analog-to-digital converter (ADC): flash comparator core (bipolar) with CMOS logic

BiCMOS at Advanced Nodes (130nm/90nm):
- 130nm BiCMOS: mature, production volume
- 90nm BiCMOS: limited availability (not all foundries offer)
- Scaling challenge: bipolar isolation degrades (leakage current increases)
- Alternative: pure CMOS with careful design (CMOS speed now competes with older BiCMOS)

CMOS-Only Alternative Trend:
- CMOS fT scaling: modern CMOS (28nm FinFET) approaching BiCMOS performance
- Cost benefit: CMOS single-process vs BiCMOS multi-process overhead
- Integration: CMOS-only higher density (no collector sinker area waste)
- Decision: BiCMOS justified for low-volume, extreme performance; CMOS default for cost/volume

BiCMOS Foundry Roadmap:
- Existing: TSMC (older nodes), GlobalFoundries, older processes
- Future: scaling stopped at 28nm BiCMOS (industry consensus)
- Niche survival: specialized RF/analog nodes (not advancing with digital roadmap)

BiCMOS remains relevant for analog/RF applications requiring extreme performance, though CMOS scalability eroding its competitive advantage as technology advances.