Bipolar Ecl 1960s Advance to Mecl Ii

# Bipolar ECL Logic (1960s): Step 16 — Advancing to MECL II

Motorola's second-generation refinement, and what actually changed. MECL II, introduced in the mid-1960s, roughly doubled switching speed over MECL I without changing the fundamental current-switch topology established in Steps 2-3. This step covers what process and circuit refinements MECL II made, since the topology itself was already settled by this point in the series.

## 1. What Got Faster, and Why
MECL II's speed gain came primarily from two sources that do not require any new circuit topology: faster bipolar transistors (improved epitaxial planar processing reduced base width and junction capacitance, raising f_T and directly shortening the transit-time term identified in Step 9's delay breakdown), and tighter internal biasing that reduced the voltage swing and node capacitance the current switch had to charge on each transition, within the noise-margin budget worked out in Step 13. Typical MECL II gate propagation delays reached roughly 1-2 nanoseconds, a meaningful step down from MECL I's 2-8 nanosecond range, achieved by optimizing the same circuit this series has already fully derived rather than inventing a new one.

## 2. Real Diagram: MECL I vs. MECL II Delay and Process Comparison

MECL I vs. MECL II Delay and Process Comparison faster transistors and tighter biasing, same topology MECL I 2-8 ns MECL II 1-2 ns gate delay (ns) power per gate stayed roughly flat — the speed gain used the "more current" lever

## 3. The Tradeoff MECL II Did Not Solve
MECL II's speed gain did not come with a power reduction — if anything, the faster transistors and tighter biasing kept per-gate power draw in roughly the same 1.5-3 milliwatt range as MECL I, consistent with the state-independent power mechanism from Step 11: making the current switch faster generally means either more current or less capacitance, and MECL II mostly used the 'more current' lever. This left the power/speed tradeoff unresolved going into the next generation, MECL 10K, which took a different approach by prioritizing manufacturability, interfacing ease, and moderate power over raw speed — the subject of Step 17.

## 4. Companion Diagram: Stage Sequence and Trend Summary

Advancing to MECL II (1966) refined transistor geometry and speed enhancement to 4ns SHRUNK BASE WIDTH Planar Silicon Substrate Input Switch Q1 Base Drive ~0.8V Differential Pair Shallower diffusion depths and narrower emitter stripes reduced transit time. 4ns PROPAGATION Planar Silicon Substrate Constant Current Sink I_EE Propagation delay halved to 4ns with comparable power per gate (~25mW). IMPROVED PINOUT Planar Silicon Substrate Emitter Follower Z_out ≈ 5-10Ω 50Ω Line Buffer Standardized dual-in-line packaging with dedicated V_CC ground pins. Key Circuit Architecture Takeaway MECL II solidified Motorola's leadership in high-speed computing logic during the mid-1960s.

## Advancing to MECL II's Place in the Process Lineage
This is step 16 of 20 in the Bipolar ECL Logic (1960s) series, covering MECL II's process- and biasing-driven speed improvement over MECL I without a change to the underlying current-switch topology.

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