Bosch Process

The Bosch process, specifically designated as time-multiplexed pulsed Deep Reactive Ion Etching (DRIE), is a time-multiplexed anisotropic silicon plasma-etching method used for deep and high-aspect-ratio features. Achievable angle, depth and aspect ratio are tool-, mask-, loading-, geometry- and recipe-specific by rapidly alternating between conformal fluorocarbon passivation deposition and directional floor-sputter radical etching sub-steps. In advanced ICP DRIE etch tools from Lam Research (Pegasus, Syndion), Applied Materials (Centris Sym3), and Tokyo Electron (Tactras), the Bosch process enables critical silicon micromachining across Through-Silicon Vias (TSVs, $D = 100.0\ \mu\text{m}$, $W = 10.0\ \mu\text{m}$), MEMS inertial sensors (gyroscopes, accelerometers), DRAM deep trench capacitors ($AR > 60:1$), and 3D silicon interposers. The process mechanism operates through two cyclic sub-steps repeated hundreds to thousands of times: (1) a Passivation Phase, in which octafluorocyclobutane ($C_4 F_8$) plasma generates reactive fluorocarbon radicals ($CF_2^\bullet$) that conformally deposit a thin Teflon-like polymer film ($n-(CF_2)_x$, thickness $d_{\text{poly}} = 5.0\text{ nm}$ to $15.0\text{ nm}$) over all exposed surfaces, and (2) an Etch Phase, in which sulfur hexafluoride ($SF_6$) plasma supplies fluorine radicals ($F^\bullet$) and directional positive ions ($SF_x^+, F^+$). RF bias voltage ($V_{\text{bias}} = 150\text{ V}$ to $350\text{ V}$) accelerates ions perpendicular to the wafer, selectively sputtering away the floor polymer film ($t_{\text{clear}} = 0.15\text{ s}$) while leaving sidewall polymer intact. Fluorine radicals spontaneously react with exposed floor silicon to produce volatile $SiF_4 \uparrow$ ($Si + 4F^\bullet \to SiF_4 \uparrow$), enabling rapid silicon removal while targeting useful selectivity to underlying silicon dioxide or photoresist masks ($S_{\text{Si:mask}} > 200:1$). Managed across leading-edge fabs including TSMC, Intel, Samsung, SK hynix, Micron, and IBM using TCAD profile simulation from Synopsys (Sentaurus Etch) and Coventor (SEMulator3D), unmitigated Bosch DRIE causes sidewall scalloping defects ($h_{\text{scallop}} = 50.0\text{ nm}$ to $150.0\text{ nm}$), aspect-ratio-dependent etch lag, profile bowing, and notch formation at dielectric etch stop interfaces.

The sidewall scallop is not a defect but the direct signature of the loop: each pass etches laterally for as long as it takes the next passivation layer to arrive, so scallop height and etch rate are the same trade made twice.

Conformal fluorocarbon polymer deposition kinetics govern sidewall protection in the Bosch process. In the passivation sub-step, octafluorocyclobutane ($C_4 F_8$) gas is ionized in a high-density Inductively Coupled Plasma (ICP, source power $W_{\text{ICP}} = 2500\text{ W}$, pressure $P = 25\text{ mTorr}$). Electron-impact dissociation breaks $C_4 F_8$ into $CF_2^\bullet$ radicals ($C_4 F_8 + e^- \to 4 CF_2^\bullet + e^-$), which adsorb onto all exposed wafer surfaces with a sticking probability $\gamma_{\text{stick}} = 0.12$. Polymer growth rate $R_{\text{poly}}$ scales directly with radical concentration $C_{CF_2}$:

Where $\rho_{\text{poly}} = 2.15\text{ g/cm}^3$ is the density of the fluorocarbon polymer film, and $s_0 = 0.10$ is the initial sticking coefficient. During a typical passivation step duration ($t_{\text{pass}} = 1.0\text{ s}$), a conformal polymer film of thickness $d_{\text{poly}} = 8.0\text{ nm}$ is deposited uniformly across both horizontal feature floors and vertical sidewalls.

Directional ion sputtering clears floor polymer to initiate isotropic fluorine radical silicon etching. When the chamber gas supply switches to $SF_6$ ($t_{\text{switch}} < 50\text{ ms}$), RF bias power ($W_{\text{bias}} = 120\text{ W}$, $V_{\text{bias}} = 220\text{ V}$) accelerates directional $SF_x^+$ and $F^+$ ions normal to the wafer surface. Directional ion flux $J_{\text{ion}}$ preferentially sputters away the fluorocarbon polymer at the trench floor ($\theta = 0^\circ$). The polymer clearance time $t_{\text{clear}}$ is:

For $d_{\text{poly}} = 8.0\text{ nm}$ and ion sputtering yield $Y_{\text{sputter}} = 1.8\text{ monomer/ion}$, clearance occurs in $t_{\text{clear}} = 0.15\text{ s}$. Once floor silicon is exposed, fluorine radicals ($F^\bullet$) spontaneously react with silicon to form volatile $SiF_4 \uparrow$ ($Si + 4F^\bullet \to SiF_4 \uparrow$). Because sidewalls ($\theta = 90^\circ$) experience zero normal ion flux ($J_{\text{ion,side}} \approx 0$), the sidewall polymer film remains intact, preventing lateral chemical etching.

Periodic chemical etch sub-steps create sidewall scallop undulations. The isotropic chemical etch phase of exposed floor silicon continues for the remainder of the etch step duration ($t_{\text{etch}} - t_{\text{clear}} = 1.35\text{ s}$). Isotropic radical etching expands outward in a hemispherical wave, creating a characteristic crest-and-trough sidewall pattern called a scallop. Scallop height $h_{\text{scallop}}$ and cycle depth $\Delta D_{\text{cycle}}$ are expressed as:

For an isotropic etch rate $ER_{\text{iso}} = 1.10\ \mu\text{m/min} = 18.3\text{ nm/s}$, scallop height per cycle is $h_{\text{scallop}} = 18.3\text{ nm/s} \times 1.35\text{ s} = 24.7\text{ nm}$. Scallop pitch $\lambda_{\text{scallop}}$ equals the vertical silicon depth etched per cycle ($\Delta D_{\text{cycle}} = 320.0\text{ nm}$). Fast gas switching valves ($t_{\text{step}} = 0.4\text{ s}$) reduce scallop height to $h_{\text{scallop}} < 8.0\text{ nm}$ for smooth Through-Silicon Via (TSV) liners.

Parameter ramping algorithms dynamically adjust etch step durations to offset Knudsen diffusion limitations in deep trenches. As trench depth increases from $D = 10.0\ \mu\text{m}$ to $D = 150.0\ \mu\text{m}$, Knudsen transport limitations reduce radical supply to the feature floor (RIE lag). Advanced process control (APC) counters RIE lag by dynamically ramping SF6 etch step duration ($t_{\text{etch}} = 1.5\text{ s} \to 3.2\text{ s}$) and ICP source power ($W_{\text{ICP}} = 2500\text{ W} \to 4200\text{ W}$) linearly with cycle count $N$, partly compensating for transport loss. Ramping does not guarantee constant rate and can trade bow, mask erosion, charging and roughness against depth.

High chemical selectivity to the etching mask enables extreme depth aspect ratios while maintaining top critical dimensions. Silicon-to-oxide selectivity $S_{\text{Si:SiO2}} = ER_{\text{Si}} / ER_{\text{SiO2}} = 210:1$ allows a thin $1.0\ \mu\text{m}$ oxide hard mask to withstand $500\text{ etch cycles}$ down to $D = 150.0\ \mu\text{m}$. Sidewall polymer passivation prevents lateral mask undercut, preserving top feature opening width ($W_{\text{top}} = 10.0\ \mu\text{m} \pm 0.15\ \mu\text{m}$) throughout the process.

Read the Bosch Process through a *time-multiplexed polymer passivation and floor-sputter directional etching* lens rather than a *simple continuous etch* lens. In 3D semiconductor manufacturing, the Bosch process is not a static two-step recipe; it is a highly dynamic kinetic equilibrium between fluorocarbon radical surface polymerization, directional ion sputtering, and chemical radical transport. Every parameter in modern DRIE tools — from piezoelectric gas valve switching speeds and dual-frequency RF bias generators to parameter ramping APC algorithms and turbomolecular pumping speeds — represents the active tuning of cyclical surface reactions. Master these surface polymerization kinetics and time-multiplexed switching dynamics, and your process integration architectures will consistently achieve ultra-high-aspect-ratio vertical trench profiles across sub-2nm GAA NanoSheet contacts, MEMS sensors, and 3D Through-Silicon Vias (TSVs).

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## Passivation Polymer Film Deposition Kinetics

Conformal fluorocarbon polymer film ($n-(CF_2)_x$, $d_{\text{poly}} = 8.0\text{ nm}$) deposition during $C_4F_8$ plasma sub-step ($t_{\text{pass}} = 1.0\text{ s}$).

Fluorocarbon radical polymerization ($C_4F_8 \to 4 CF_2^\bullet$) forms $d_{\text{poly}} = 8.0\text{ nm}$ conformal Teflon film in $t_{\text{pass}} = 1.0\text{ s}$.

During the passivation step, $C_4 F_8$ gas flows into the ICP source chamber at $180\text{ sccm}$. High ICP source power ($W_{\text{ICP}} = 2500\text{ W}$) dissociates $C_4 F_8$ into $CF_2^\bullet$ radicals. Polymerization occurs on exposed silicon surfaces according to surface radical flux $J_{CF_2} = \frac{1}{4} C_{CF_2} \bar{v}_{\text{thermal}}$. The resulting Teflon-like polymer film ($n-(CF_2)_x$) exhibits high chemical resistance against isotropic fluorine radical attack. Conformal step coverage $\theta_{\text{coverage}} = d_{\text{side}} / d_{\text{top}} > 0.92$ is maintained by optimizing chamber pressure ($P = 25\text{ mTorr}$) to ensure radical mean free path $\lambda_{\text{mfp}}$ exceeds trench opening width.

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## Anisotropic Directional Ion Floor Polymer Clearing & Isotropic Etch

Directional ion sputtering ($V_{\text{bias}} = 220\text{ V}$, $t_{\text{clear}} = 0.15\text{ s}$) clears floor polymer, allowing $F^\bullet$ radicals to etch silicon ($Si + 4F^\bullet \to SiF_4 \uparrow$).

RF bias voltage ($V_{\text{bias}} = 220\text{ V}$) drives directional ion floor sputtering ($t_{\text{clear}} = 0.15\text{ s}$), exposing silicon to $F^\bullet$ radicals.

In the etch phase, $SF_6$ gas is introduced at $450\text{ sccm}$. ICP source power ($W_{\text{ICP}} = 2800\text{ W}$) generates high fluorine radical density ($n_F = 1.2 \times 10^{15}\text{ cm}^{-3}$). Applied RF bias voltage ($V_{\text{bias}} = 220\text{ V}$) creates a directional ion sheath. Positive ions ($SF_5^+, F^+$) strike horizontal surfaces with normal energy $E_{\text{ion}} = 220\text{ eV}$, sputtering the floor polymer film in $t_{\text{clear}} = 0.15\text{ s}$. Exposed floor silicon undergoes rapid chemical etching by $F^\bullet$ radicals ($Si + 4F^\bullet \to SiF_4 \uparrow$). Sidewalls retain more polymer because the sheath directs most ion momentum toward horizontal surfaces; angular spread, charging and scattering still expose walls to some bombardment.

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## Sidewall Scallop Height & Pitch Formation Mechanics

Isotropic radical etching during $(t_{\text{etch}} - t_{\text{clear}})$ creates periodic sidewall scallops ($h_{\text{scallop}} = 24.7\text{ nm}$, pitch $\lambda_{\text{scallop}} = 320.0\text{ nm}$).

Scallop height $h_{\text{scallop}} = 24.7\text{ nm}$ scales directly with isotropic etch time $(t_{\text{etch}} - t_{\text{clear}})$.

Repeated cycling creates periodic wave-like undulations along trench sidewalls. Each cycle leaves a scallop peak where the protective polymer terminated and a scallop trough where isotropic radical etching expanded laterally. Scallop peak-to-valley height $h_{\text{scallop}}$ determines sidewall roughness. In 3D packaging TSVs, excessive scallop roughness ($h_{\text{scallop}} > 50.0\text{ nm}$) causes void formation during subsequent $SiO_2$ barrier and $Cu$ seed physical vapor deposition (PVD). Reducing step time via fast switching valves ($t_{\text{step}} = 0.4\text{ s}$) produces smooth sidewalls ($h_{\text{scallop}} < 8.0\text{ nm}$), ensuring void-free metalization.

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## Parameter Ramping APC and Fast Switching Valves

Parameter ramping APC increases $t_{\text{etch}}$ ($1.5\text{ s} \to 3.2\text{ s}$) and $W_{\text{ICP}}$ ($2500\text{ W} \to 4200\text{ W}$) to eliminate RIE lag in deep trenches ($D > 100\ \mu\text{m}$).

Dynamic parameter ramping APC maintains constant net etch rate ($7.5\ \mu\text{m/min}$) down to $D = 150.0\ \mu\text{m}$.

As the trench etches deeper into the silicon substrate, Knudsen diffusion conductance losses reduce fluorine radical transport to the feature floor (RIE lag). Without intervention, net etch rate drops by $> 60\%$. Advanced Process Control (APC) implements linear parameter ramping algorithms:

Where $N$ is cycle count, $\alpha_{\text{ramp}} = 0.0034\text{ s/cycle}$, and $\beta_{\text{ramp}} = 3.4\text{ W/cycle}$. Dynamic ramping offsets radical transport bottlenecks, ensuring identical etch depth increment $\Delta D_{\text{cycle}} = 320.0\text{ nm}$ per cycle throughout a $500\text{-cycle}$ process.

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## Silicon-to-Mask Selectivity and High-Aspect-Ratio TSV Profiles

High silicon-to-mask selectivity ($S_{\text{Si:SiO2}} > 200:1$) enables deep TSVs ($AR > 40:1$, depth $D = 150.0\ \mu\text{m}$).

Silicon-to-oxide selectivity $S_{\text{Si:SiO2}} = 210:1$ restricts hard mask erosion to $< 750\text{ nm}$ over $150.0\ \mu\text{m}$ deep TSV etches.

High chemical selectivity to the etching mask is essential for deep DRIE. Thermal $SiO_2$ or PECVD oxide hard masks resist fluorine radical attack because silicon-oxygen bonds ($E_{\text{bond}} = 8.2\text{ eV}$) require directional ion energy to break. Fluorocarbon polymer deposition during the passivation phase further shields the oxide mask. Overall selectivity $S_{\text{Si:SiO2}} = ER_{\text{Si}} / ER_{\text{SiO2}} = 210:1$ allows a thin $1.0\ \mu\text{m}$ oxide mask to pattern a $150.0\ \mu\text{m}$ deep silicon TSV trench. At the underlying dielectric etch-stop interface ($SiO_2$ or $Si_N_4$), switching to low-frequency pulsed bias ($f_{\text{bias}} = 100\text{ Hz}$) prevents charging-induced ion deflection and eliminates floor notch formation.

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## Metrology Qualification: HR-STEM and Inline 3D OCD Scallop Audit

Inline Mueller matrix 3D OCD scatterometry and cross-sectional HR-STEM qualify Bosch DRIE scallop height $h_{\text{scallop}}$ and trench depth $D$.

Inline Mueller matrix 3D Optical Critical Dimension (OCD) scatterometry and HR-STEM cross-sections verify Bosch DRIE profile fidelity ($\theta_{\text{taper}} = 90.0^\circ \pm 0.3^\circ$) across TSMC, Intel, Samsung, SK hynix, Micron, and IBM production wafers, modeled in Synopsys Sentaurus and Coventor SEMulator3D.

Inline Mueller matrix Optical Critical Dimension (OCD) scatterometry extracts deep trench profiles by measuring multi-wavelength spectroscopic polarization signatures across periodic target arrays. Raw ellipsometric parameters ($\Psi, \Delta$) are reconstructed using rigorous coupled-wave analysis (RCWA) parameterized by a multi-segment profile vector:

Extracted depth profiles achieve non-destructive precision $\sigma < 0.25\text{ nm}$ at throughputs exceeding $110\text{ wafers/hour}$. Output metrology data feeds directly into run-to-run Advanced Process Control (APC) models on Lam Research Pegasus, Applied Materials Centris Sym3, and Tokyo Electron Tactras etchers, automatically updating parameter ramping slopes ($\alpha_{\text{ramp}}, \beta_{\text{ramp}}$) to hold scallop height $h_{\text{scallop}} < 10.0\text{ nm}$ and guarantee $> 99.8\%$ functional TSV yield in 3D advanced packaging architectures.