Buried Power Rails

Backside power delivery networks (BSPDN) move the power distribution grid from the front side of the wafer, where it competes with signal routing, to the back side, where it competes with nothing. The transistor layer is then contacted from both faces: signals from above through conventional BEOL, power from below through nano-scale through-silicon vias. It is the most significant change to interconnect architecture since dual damascene.

The problem it solves

In a front-side network, power travels from package bumps down through every metal level to reach the device. Each level contributes resistance, and the wide power straps on the lower levels consume routing tracks that signals need. The voltage actually reaching a cell is degraded by

\Delta V_{\text{IR}} = I_{\text{cell}} \cdot R_{\text{grid}}

and because dynamic current scales with activity while grid resistance rises as wires narrow, IR drop has been worsening every node. Backside delivery attacks $R_{\text{grid}}$ directly: the backside metal is built on a free surface, so it can be thick and wide, with sheet resistance an order of magnitude below a comparable front-side layer. Reported IR-drop improvements are in the range of 5 to 10 times.

Buried power rails

The enabling front-side change is the buried power rail. Instead of running $V_{DD}$ and $V_{SS}$ as M0/M1 wires above the fins, the rail is sunk into a trench in the shallow-trench isolation, below the device layer, filled with a refractory metal — typically tungsten or ruthenium, chosen because they survive the full thermal budget that follows. The rail is then contacted from beneath by a nano-TSV.

Removing the rails from the cell's metal stack is what unlocks track-height scaling. A standard cell's width is quantised in routing tracks, and two of them were historically spent on power:

T_{\text{cell}} = T_{\text{signal}} + T_{\text{power}} \;\longrightarrow\; T_{\text{cell}} \le 5T

Moving power below takes the cell from 6T toward 5T and below, a direct area reduction of roughly 15 to 20 percent that costs nothing in transistor performance.

Nano-TSV and the back-to-front contact

The via that joins the two faces is not a classical TSV. Classical package-level TSVs are 5 to 10 μm across; a nano-TSV is a few hundred nanometres, with aspect ratios around 10:1, and it must land on a buried rail only tens of nanometres wide. The process sequence is bonding to a carrier, grinding and etching the device wafer down to a few hundred nanometres with a buried etch-stop layer, then patterning and filling the vias from beneath.

Two parameters dominate the electrical result. The via resistance itself scales as

R_{\text{nTSV}} = \frac{\rho\, L}{A} = \frac{4\rho\, L}{\pi d^{2}}

so halving the diameter quadruples resistance, and the drive to shrink the via for density fights the drive to widen it for conduction. Alongside it sits the back-to-front contact resistance at the nano-TSV to rail interface, governed by the specific contact resistivity $\rho_c$ over a contact area that is by construction tiny:

R_{c} = \frac{\rho_c}{A_{c}}

This interface, not the via body, is usually the limiting resistance in a BSPDN, and it is why low-temperature silicide and barrier metallurgy on the backside are active process-development areas.

The thermal penalty

The gain is not free. In a conventional die, heat generated in the device layer conducts down through the silicon substrate to the package and heat sink. Backside power delivery removes most of that substrate and replaces it with a metal network and bonding interfaces, so the junction-to-case thermal resistance rises:

\theta_{jc} = \frac{T_j - T_c}{P}, \qquad \theta_{jc}^{\text{BSPDN}} > \theta_{jc}^{\text{conventional}}

The device layer ends up thermally sandwiched, and the self-heating that the improved IR drop was meant to relieve partly returns as a temperature rise. Because carrier mobility degrades and leakage climbs with temperature, and because electromigration lifetime carries an Arrhenius term, the thermal penalty must be budgeted explicitly rather than treated as a second-order effect. Practical designs recover margin through thicker backside metal, deliberate thermal vias, and placement that spreads high-activity blocks.

Parameter	Front-side PDN	Backside PDN
Grid resistance	baseline	5–10× lower
Cell track height	6T and above	5T and below
Routing congestion	power competes with signal	signal owns the BEOL
$\theta_{jc}$	baseline	higher — substrate removed
Process complexity	mature	wafer bonding, thinning, backside litho

Where it stands

BSPDN entered production at the 2 nm generation and is treated as mandatory beyond it, because the alternative — continuing to spend routing tracks and IR-drop budget on a front-side grid — does not scale. The remaining engineering difficulty is not whether the power reaches the transistors but whether the heat can leave.

Buried Power Rails

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