C-V Curve

C-V curve (capacitance-voltage) measures capacitance across MOS structures vs. applied voltage — revealing oxide thickness, interface trap density, doping profiles, and threshold voltage through the characteristic accumulation-depletion-inversion behavior.

What Is C-V Curve?

• Definition: Plot of capacitance vs. gate voltage for MOS structure.
• Measurement: AC capacitance at various DC bias voltages.
• Purpose: Characterize gate stack quality and MOS interface.

Why C-V Curves Matter?

• Oxide Thickness: Directly measured from accumulation capacitance.
• Interface Quality: Trap density affects C-V shape.
• Doping Profile: Extracted from depletion region.
• Threshold Voltage: Estimated from C-V characteristics.

C-V Curve Regions

Accumulation: High positive voltage (NMOS), maximum capacitance (Cox).
Depletion: Moderate voltage, decreasing capacitance.
Inversion: Negative voltage (NMOS), minimum capacitance.
Flat-Band: Voltage where bands are flat, indicates oxide charges.

Key Parameters Extracted

Oxide Capacitance (Cox): Maximum capacitance in accumulation.
Oxide Thickness (tox): Calculated from Cox = εox·A/tox.
Flat-Band Voltage (VFB): Indicates fixed oxide charges.
Threshold Voltage (Vth): Approximate transistor turn-on voltage.
Interface Trap Density (Dit): From C-V stretch-out and hysteresis.
Doping Concentration: From depletion capacitance slope.

Measurement Types

High-Frequency C-V: Standard measurement (1 MHz), minority carriers can't follow.
Quasi-Static C-V: Slow sweep, minority carriers respond, reveals Dit.
Multi-Frequency: Vary frequency to separate interface traps.
Hysteresis: Forward and reverse sweeps reveal charge trapping.

What C-V Curves Reveal

Oxide Quality: Smooth C-V indicates good oxide.
Interface Traps: Stretch-out and hysteresis indicate Dit.
Fixed Charges: VFB shift from ideal indicates oxide charges.
Mobile Ions: Temperature-dependent VFB shift.
Doping Profile: Depletion region slope reveals doping.

Applications

Process Monitoring: Track oxide deposition quality.
Interface Characterization: Quantify interface trap density.
Reliability Testing: Monitor charge trapping under stress.
Model Extraction: Validate SPICE model parameters.

Analysis Techniques

Cox Extraction: Measure capacitance in strong accumulation.
VFB Extraction: Find voltage where C = Cox/2 (approximately).
Dit Extraction: Compare high-frequency and quasi-static C-V.
Doping Extraction: Analyze 1/C² vs. V in depletion.

C-V Curve Factors

Oxide Thickness: Thinner oxides have higher Cox.
Interface Quality: Poor interface increases Dit, stretches C-V.
Oxide Charges: Fixed charges shift VFB.
Doping: Affects depletion width and C-V shape.
Temperature: Affects carrier response and trap occupancy.

Interface Trap Density (Dit)

Low Dit: Sharp C-V transition, low hysteresis.
High Dit: Stretched C-V, large hysteresis.
Typical Values: 10¹⁰ - 10¹¹ cm⁻²eV⁻¹ for good interfaces.
Impact: High Dit reduces mobility, increases noise.

Reliability Implications

BTI: Charge trapping shifts VFB and Vth over time.
TDDB: Interface degradation precedes oxide breakdown.
Radiation: Creates interface traps, shifts VFB.
Hot Carriers: Generate interface traps, increase Dit.

Advantages: Non-destructive, comprehensive gate stack characterization, sensitive to interface quality, doping profile extraction.

Limitations: Requires large-area capacitors, frequency-dependent, interpretation requires expertise.

C-V curve analysis is gate stack health check — confirming insulating layers and interfaces behave as designed, critical for transistor performance and reliability.