Cfet Logic Confront the Shared Gate Versus Independent Gate Question

# CFET (Complementary FET): Step 8 — Confront the Shared-Gate Versus Independent-Gate Question

## 1. A Question the Stack Forces

With the NMOS and PMOS channels isolated from each other by the middle dielectric (Step 7), the gate structure that wraps each device's sheets still has to be formed somewhere relative to that isolation — and designers face a genuine choice: let the top device's gate and the bottom device's gate be electrically continuous, forming one shared gate structure that wraps both stacks as if they were a single tall column, or keep the two gates electrically independent, each with its own separate contact, even though they are structurally stacked in the same column.

## 2. The Case for a Shared Gate

A shared gate is structurally simpler: one gate-fill step, one gate contact, and no need to route two separate gate signals to two different heights within the same column. For a plain inverter — where the input signal legitimately needs to drive both the NMOS and PMOS gate at once anyway — a shared gate is not just simpler, it is exactly the connectivity the circuit already wants, and several early CFET demonstration devices in the research literature have used shared-gate inverters specifically because that case needs no additional gate routing at all.

## 3. The Case for Independent Gates

Many logic functions beyond the plain inverter need the top and bottom device's gates driven by different signals, not the same one — a transmission gate, a multiplexer input, or any gate topology where the NMOS and PMOS paths are not simply mirrored. A shared gate forecloses those circuit topologies entirely for any cell built on it, which is why independent, separately contacted top and bottom gates are necessary for a general-purpose standard-cell library rather than only for inverter-like cells. Step 9 picks up exactly why this constraint on design-flow flexibility matters enough to justify the added complexity of independent gate contacts.

## 4. Where the Research Points

Reported CFET research and development work pursues both options depending on the target circuit: shared gates for area-optimized inverter-class cells, independent gates for anything requiring more general logic flexibility. Neither is described as a universal answer, and a mature CFET standard-cell library would likely offer both gate configurations as distinct cell variants, chosen per logic function the way current libraries already offer multiple drive-strength variants of the same gate.