Charged Device Model

The charged device model (CDM) is an ESD test standard that simulates the single most common real-world electrostatic discharge event in manufacturing — a chip package itself accumulating charge from ordinary handling, sliding, or automated pick-and-place, then discharging that entire stored charge in under a nanosecond the instant any pin touches a grounded surface. Its extreme speed is exactly what makes it dangerous: CDM events can destroy a chip's most delicate internal structures without leaving any visible external evidence that anything happened at all.

CDM: The Chip Discharges Itself Unlike HBM, where a charged person touches the chip, here the chip is already the charged object. HOW IT HAPPENS package charges from handling any pin touches ground entire stored charge exits through that one pin, < 1ns THE WAVEFORM 5-15A peak rise ~100-250ps, duration ~1-2ns far faster and higher-current than HBM's milder pulse CLASSIFICATION LEVELS C1 (125V) · C2 (250V) · C3 (500V) · C4 (750V) · C5 (1000V) — per ANSI/ESDA/JEDEC JS-002. Protecting against CDM specifically requires careful power-clamp and core-clamp design on-chip. CDM is the #1 cause of ESD damage in automated assembly lines, not from any outside human contact.

CDM's charging mechanism is fundamentally different from human-body-model ESD, because in CDM the chip itself is the charged object rather than a person who then touches it. Ordinary handling in automated manufacturing — a package sliding along a tray, friction during pick-and-place robotic handling, simple contact with charged surfaces — can accumulate real static charge directly on the package itself, with no human involvement at all. That charge sits stored across the entire package until some pin makes contact with a grounded surface, at which point the whole accumulated charge discharges through whichever pin happened to touch ground first.

The discharge waveform's extreme speed — rise time in the range of 100 to 250 picoseconds, total duration only one to two nanoseconds, with peak current reaching 5 to 15 amps — is what makes CDM so disproportionately damaging compared to slower ESD models. This pulse is both faster and carries higher peak current than the human-body-model discharge, concentrating an enormous amount of energy into an extraordinarily short time window. Protection circuitry designed to handle a slower, lower-current discharge event can be completely inadequate against CDM's much sharper, faster pulse, which is exactly why CDM requires its own dedicated protection design consideration rather than simply reusing whatever protects against other ESD models.

Internal damage without visible external evidence is CDM's most insidious characteristic, because the fast discharge can destroy thin gate oxides internally while leaving the package looking completely undamaged from the outside. A CDM event's energy concentrates specifically at whatever internal structure happens to sit along the discharge path from the triggering pin to wherever the charge ultimately dissipates — often a transistor's thin gate oxide, which can suffer catastrophic, permanent damage from this brief but intense current surge. Because nothing about the package's external appearance changes, a CDM-damaged device can pass visual inspection cleanly while harboring a latent defect that may only manifest as a failure much later, during actual field use.

Classification levels — C1 through C5, corresponding to 125 through 1000 volts — give manufacturers a standardized way to specify and verify how much CDM stress a given device can actually tolerate before failing. Testing under the ANSI/ESDA/JEDEC JS-002 standard applies controlled CDM discharges at each specified voltage level, confirming whether a device survives that level of stress without damage. A device rated at a higher classification level has demonstrated tolerance to a correspondingly larger stored charge and discharge event, giving designers and manufacturers a concrete, comparable specification to design assembly-line handling procedures and protection circuitry around.

CDM being the number-one cause of ESD damage specifically in automated assembly lines, rather than from human handling, reflects exactly where and how modern manufacturing actually exposes devices to this failure mode. Automated pick-and-place equipment, feeder trays, and high-speed handling mechanisms create exactly the friction and contact conditions that charge a package, and the sheer volume and speed of automated handling in a modern assembly line means CDM-triggering contact events happen constantly, at scale that manual human handling never approached. This is precisely why CDM protection design and assembly-line electrostatic control — not just general ESD awareness training for human operators — have become central, dedicated concerns in modern semiconductor manufacturing.

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