Chip Design
Chip design is the work of turning an intended behaviour into a set of polygons a foundry can print. It proceeds as a ladder of representations — each rung more physical than the one above it, each one discarding information the rung below can no longer recover. Almost everything that determines a chip's power, speed, area and cost is fixed on this ladder, long before a wafer is exposed to light.
Every decision on the ladder is one trade, priced in three currencies. Power, performance and area — PPA — is the governing constraint, and the three cannot be optimised independently. Buying speed with a low-threshold cell library costs leakage. Buying area by sharing a datapath costs throughput. Buying power with aggressive clock gating costs verification effort and timing complexity. Two further currencies never appear in the acronym and frequently decide the project: schedule, and the mask set, which at a leading node runs into tens of millions of dollars before a single good die exists.
Verification is the majority of the project, not a phase at its end. On a large SoC, verification routinely consumes more engineering effort than design does. It runs as several methods in parallel: directed and constrained-random simulation measured by functional coverage, formal property checking for blocks where exhaustive proof is feasible, and hardware emulation for booting real software against the design before silicon exists. The economics are brutal and simple — a functional bug caught in RTL costs an afternoon, and the same bug found in silicon costs a respin.
Timing closure is where the schedule actually disappears. A path meets setup if its data arrives before the capture edge needs it, and meets hold if it does not arrive so early that it corrupts the same edge that launched it. Static timing analysis checks every path without simulating vectors — but it must do so across process, voltage and temperature corners, across parasitic extraction corners, and across operating modes such as functional, scan and low-power. Multiply those together and a modern signoff runs hundreds of scenarios. Variation modelling has had to become statistical too, moving from flat on-chip variation derating to AOCV and then parametric POCV, because a single pessimistic margin applied everywhere makes a design that cannot close at all.
Effects that were once second-order now shape the floorplan. IR drop across the power grid steals voltage from cells that need it most under peak switching. Electromigration limits how much current a given wire may carry for ten years without voiding. Crosstalk between adjacent nets shifts timing in ways a lumped model misses. Thermal gradients change transistor behaviour across the die. None of these are checks you pass at the end — they set where the power grid goes, how wide the straps are and where the hot blocks may sit, which is why backside power delivery is being adopted: it moves the power network off the signal layers entirely.
The PDK is the contract with the foundry, and it is not negotiable. A process design kit supplies the standard cell libraries with characterised timing and power, the threshold-voltage flavours a designer trades speed against leakage with, the parasitic extraction decks, and the DRC and LVS rule sets that define what the fab will and will not print. Design rule checking confirms the layout is manufacturable; layout-versus-schematic confirms it is still the circuit that was verified. Tapeout is not the moment a layout looks finished — it is the moment a complete signoff package, GDSII or OASIS plus every clean check, is handed over.
| Stage | What it commits | Hands on | If it is wrong |
|---|---|---|---|
| Architecture | Performance and power budget, partitioning | Microarchitecture spec | Nothing downstream can recover it |
| RTL | Cycle-accurate behaviour | Verilog / VHDL source | Caught by verification, or not at all |
| Verification | Confidence, not correctness | Coverage closure sign-off | Escapes become respins |
| Synthesis | Gate choice, Vt mix, initial timing | Gate-level netlist | Re-run, hours to days |
| Floorplan | Block placement, power grid, pin access | Physical constraints | Late changes ripple through routing |
| Place and route | Real geometry, real parasitics | Routed layout | Congestion or timing loops |
| Signoff | STA, DRC, LVS, IR, EM, DFT coverage | Tapeout package | A mask set spent on a bad die |
Modern design is closer to assembly than to drawing. Very little of a large SoC is drawn from scratch: CPU and GPU cores, memory controllers, PHYs and interface blocks arrive as licensed or internally reused IP, hardened or soft. The integration work — clock and reset topology, power domains, interconnect fabric, verification of the assembled whole — is where the effort now sits. Chiplets extend this off the die: UCIe standardises a die-to-die interface so a package can combine blocks from different processes, letting the parts that do not benefit from a leading node stay on a mature one.
Read chip design through a *commitment* lens rather than a *tool* lens: the flow is not a pipeline of software so much as a sequence of decisions of decreasing reversibility, and each stage's real job is to discover a problem while it is still cheap to fix. A team is not judged on how fast it can run place and route. It is judged on how early it finds the thing that would otherwise have been found in silicon.