Chiplet Interconnect
Chiplet Interconnect Standards and Architecture encompasses the physical interface, protocol, and packaging technologies that enable multiple semiconductor dies (chiplets) to communicate within a single package — with UCIe (Universal Chiplet Interconnect Express) emerging as the industry standard for die-to-die communication, defining electrical specifications, protocol layers, and packaging requirements to enable a plug-and-play chiplet ecosystem.
Why Chiplet Interconnects Matter:
The chiplet model disaggregates monolithic SoCs into smaller, specialized dies (compute, I/O, memory, accelerator) that are assembled in a package. This requires die-to-die (D2D) links that are:
- High bandwidth: >1 TB/s aggregate for AI accelerators
- Low latency: <2ns for cache-coherent communication
- Energy efficient: <0.5 pJ/bit (100× better than off-package links)
- Standardized: Enable mixing chiplets from different vendors/processes
UCIe (Universal Chiplet Interconnect Express):
UCIe 1.0 (2022) and UCIe 2.0 (2024) define a layered architecture:
UCIe Physical Layer Options:
| Package Type | Bump Pitch | Data Rate | BW Density | Reach |
|---|---|---|---|---|
| Standard (organic) | 100-130μm | 4-32 GT/s | ~28 GB/s/mm | <10mm |
| Advanced (Si interposer) | 25-55μm | 4-32 GT/s | ~165 GB/s/mm | <2mm |
Advanced packaging with 25μm bump pitch provides ~6× the bandwidth density of standard packaging.
Protocol Options:
- PCIe streaming: For standard I/O communication (NIC chiplets, storage controllers)
- CXL: For cache-coherent memory expansion and memory pooling chiplets
- Custom/Raw: Proprietary protocols for vendor-specific high-bandwidth communication (e.g., AMD's Infinity Fabric, Intel's EMIB-connected tiles)
Existing Proprietary D2D Links:
| Interface | Company | BW/Link | Latency | Application |
|---|---|---|---|---|
| Infinity Fabric | AMD | 600 GB/s | ~2ns | MI300X chiplet mesh |
| EMIB | Intel | >100 GB/s | <5ns | Meteor Lake, Ponte Vecchio |
| NVLink-C2C | NVIDIA | 900 GB/s | ~5ns | Grace-Hopper |
| Lipincon | TSMC | 1.6 TB/s | <1ns | CoWoS chiplets |
| BoW (Bunch of Wires) | OCP standard | Variable | ~3ns | Open standard |
Signal Integrity Challenges:
D2D links at 16-32 GT/s across microbumps face: crosstalk between closely spaced signals (~25μm pitch), power supply noise coupling through shared substrate, impedance discontinuities at bump transitions, and thermal effects on signal propagation. Solutions include: shielding ground lines between signal lanes, equalization (CTLE + limited DFE), and careful power distribution network design on the interposer.
Chiplet interconnect standardization through UCIe is the technical foundation enabling a heterogeneous chiplet ecosystem — allowing the semiconductor industry to transition from monolithic SoC design to a modular, multi-vendor chiplet assembly paradigm where compute, memory, I/O, and accelerator dies from different companies and process nodes can be combined in a single package.