Chiplet Known Good Die
Known good die (KGD) for chiplets is the testing discipline that confirms a chiplet actually works, at full performance and with no latent defects, before it's permanently bonded into an expensive multi-die package — because once assembly happens, a bad chiplet doesn't just fail on its own, it can take the entire finished package down with it. Getting this screening wrong is one of the most expensive mistakes possible in chiplet manufacturing, since the cost of a defect discovered after assembly is no longer the cost of one die, but the cost of every die in that package.
The economic case for rigorous KGD screening comes down to one simple fact: assembly multiplies the cost of catching a bad chiplet too late. A defective die caught at wafer sort, before any packaging investment has happened, costs only that one die. The same defect, if it slips through screening and only shows up after the chiplet is permanently bonded into a multi-chiplet package alongside several other good, expensive dies, can scrap the entire assembly — meaning the real cost of a missed defect isn't the cost of one chiplet, it's the cost of everything it was packaged with. This asymmetry is exactly why KGD screening gets disproportionately more investment in a chiplet-based product than equivalent testing would in a single-die product.
KGD screening happens in at least two distinct stages, because wafer-level testing alone can't catch everything that matters. Wafer sort testing, performed while the die is still part of the whole wafer, catches most gross functional defects at the cheapest possible stage. But some defects are latent — subtle enough that they pass basic functional test but will degrade or fail later under real operating stress, temperature cycling, or extended use — and these latent defects often require additional, more rigorous package-level screening to catch reliably. Combining wafer sort with dedicated package-level screens targeting latent failure modes specifically is what distinguishes real KGD discipline from simply running the same basic functional test chiplets would get in a conventional single-die flow.
Setting KGD targets requires defining measurable, specific thresholds for performance, reliability, and defect tolerance before integration ever begins, not discovering acceptable quality after the fact. A chiplet program that waits until after assembly to figure out what "good enough" actually meant has already lost the cost advantage KGD exists to protect. Clear, quantified targets — specific performance bins, specific reliability margins, specific acceptable latent-defect rates — set in advance give the screening flow concrete pass/fail criteria to actually test against, rather than relying on engineering judgment applied inconsistently chiplet by chiplet.
Continuous process monitoring and feedback matter more in a KGD flow than in conventional single-die testing, because the stakes of a slow drift going unnoticed are higher. Inline metrology and runtime telemetry during the screening process let a team detect a gradual shift in defect rates or test escapes before it becomes a serious problem, rather than discovering it only after a batch of compromised chiplets has already been assembled into finished packages. Split-lot testing — deliberately running controlled experiments across different process conditions before committing to full-volume screening — validates that the screening process window itself is actually sound, rather than assuming a screening recipe that worked for one chiplet generation will automatically transfer cleanly to the next.
Everything learned from KGD screening needs to feed back into design rules, test runbooks, and qualification criteria, or the same categories of defects keep recurring across chiplet generations. A specific failure mode caught repeatedly during package-level screening is a signal that something upstream — a design margin, a process parameter, a test coverage gap — needs correction, not just a signal to keep screening harder. Treating KGD as a closed feedback loop, where screening results actively shape the next generation's design rules and qualification standards, is what turns known-good-die testing from a pure cost center into a genuine driver of improving chiplet yield and reliability over time.