Choosing a Chip Foundry

Choosing a chip foundry is the decision that locks in most of a chip program's cost, schedule, and risk before a single wafer is cut, because switching foundries mid-design usually means re-qualifying the process, re-running physical verification against a new rule deck, and in many cases redesigning analog and I/O blocks from scratch. A foundry is not a generic vendor swap the way a cloud provider or a contract manufacturer for a PCB might be — the process design kit, the transistor models, and the design rules are foundry-specific, so the choice made at the start of a project is effectively the choice a team lives with for the life of that chip.

The first filter is always lithography and process-node fit, because a foundry that cannot print your design at the required geometry is not a candidate at all, regardless of price. A design targeting a mature node for cost-sensitive analog or power work has no need for a fab running EUV at 5 nanometers and below, while a design chasing maximum transistor density for an AI accelerator has no workable path through a foundry stuck at 28 nanometers. Matching the node to the actual requirement, rather than defaulting to "the newest available," is usually the single biggest lever on both cost and schedule, since leading-edge EUV capacity is scarcer and more expensive than mature-node deep-ultraviolet capacity.

Cost has to be evaluated as a full program, not as a headline wafer price, because non-recurring engineering costs dominate for anything below high volume. A multi-project wafer run, where several unrelated designs share one mask set and one wafer lot, lets a small team access advanced nodes for a fraction of the cost of a dedicated run, at the price of a fixed shuttle schedule and a hard limit on die area. A dedicated engagement removes those constraints but brings mask costs that can run from the low hundreds of thousands of dollars at mature nodes into the tens of millions at the leading edge, so the right vehicle depends entirely on volume, timeline, and how much of the design is still likely to change.

Capacity and lead time matter as much as technical fit, because an allocation shortfall at a popular node can add months to a schedule no matter how good the design is. Advanced-node capacity, in particular, has repeatedly been the binding constraint on product timelines industry-wide, not wafer cost or design difficulty, so asking a prospective foundry for realistic lead times and allocation history at your target node is as important as reviewing its rule deck. Geography adds a second layer to this question, since export controls and regional supply-chain policy can affect which fabs are practically accessible to a given company regardless of technical merit.

Design-ecosystem maturity decides how much engineering time gets spent fighting the tools instead of the product. A foundry's process design kit, its qualified third-party IP (interface controllers, memory compilers, analog IP), and the maturity of its design-rule-checking and layout-versus-schematic support all determine how smoothly a design moves from RTL to a tapeout-ready GDSII file. A cheaper node with a thin, unproven PDK and little available IP can end up costing more in engineering time than a slightly pricier node with a mature ecosystem and a deep bench of pre-qualified building blocks.

The engagement model is the final variable, and it is as much a business decision as a technical one. Pure-play foundries such as TSMC and GlobalFoundries manufacture only for other companies and never compete with their own chip products, which many fabless customers prefer for confidentiality reasons; integrated device manufacturers that also design and sell their own chips can offer capacity but carry a different competitive dynamic. A short qualification run, whether a shared multi-project wafer slot or a small dedicated lot, is the standard way to validate a foundry relationship in practice before committing production volume to it.

Read foundry selection through a fit-before-price lens rather than a cheapest-wafer lens: a foundry only belongs on the shortlist once it clears the lithography and node filter, and only earns the win once cost, capacity, and ecosystem maturity are compared for that specific design — the lowest quoted wafer price from a foundry that cannot deliver the node, the volume, or the IP a design actually needs is not a lower-cost option, it is a different project with a different risk profile.