Clock Gating

Clock Gating — disabling the clock signal to registers that don't need to update, preventing useless toggling and reducing dynamic power by 20–60%.

The Problem

  • Clock network is the #1 power consumer in a digital chip (30–50% of total dynamic power)
  • Every register's clock input toggles every cycle, even if the register's data hasn't changed
  • Wasted switching = wasted power

How Clock Gating Works

Clock distribution: one edge to every flip-flop, on time and gated when idleA balanced tree delivers the same edge everywhere. Skew and jitter erode timing margin; gating stops idle toggling.Balanced H-tree (CTS)Skew & jitterClock gatingPLLbufferflip-flopequal path length → every leaf ticks togetherclk@Aclk@Bideal edgeskew Δarrival gapjitteredge wanders each cycleboth subtract from the setup / hold budgetlatchENCLK&GCLKidleblockCLKENGCLKclock stoppedEN low → no toggling → dynamic power savedTree, mesh, and CTSBuffers replicate one edge to millions offlops. H-trees and meshes equalize path lengthso every leaf ticks together — built byclock tree synthesis.Skew & jitter eat marginSkew is the spatial arrival gap between flops;jitter is cycle-to-cycle edge wander. Bothcome straight out of the setup / hold budget.Gating saves powerAn ICG cell ANDs the clock with an enable soidle blocks stop toggling. The clock net isthe biggest dynamic-power sink, so gating itwins most.
  • When EN=0: Clock is blocked → flip-flop doesn't toggle → zero dynamic power
  • When EN=1: Clock passes through → normal operation

ICG (Integrated Clock Gating) Cell

  • Latch-based clock gate: Avoids glitches by latching the enable signal
  • Standard cell libraries include optimized ICG cells
  • Synthesis tools automatically insert clock gates (RTL compiler detects when registers share enable conditions)

Levels of Clock Gating

  • RTL-level: Designer explicitly gates modules/blocks. Coarsest, most effective
  • Synthesis-level: Tool automatically groups registers with same enable. Fine-grained
  • Activity-based: Dynamic analysis identifies low-activity registers for gating

Impact

  • Typical savings: 20–40% of total chip power
  • Standard in every modern design — no chip ships without clock gating
  • EDA tools report clock gating efficiency metrics

Clock gating is the single most impactful power optimization technique in digital design — it's always the first thing to implement.

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