Compact Modeling

Compact models are simplified mathematical representations of transistor behavior used in circuit simulation (SPICE), enabling designers to predict circuit performance using foundry-provided device models. Purpose: bridge between process technology (transistor physics) and circuit design—compact models capture essential device behavior in computationally efficient form for simulating millions of transistors. Industry standard models: (1) BSIM-CMG—Berkeley model for FinFET/GAA multi-gate devices (current standard); (2) BSIM4—for planar bulk MOSFET; (3) BSIM-SOI—for SOI devices; (4) PSP—surface potential-based model (NXP/TU Delft); (5) HiSIM—Hiroshima model. Model components: (1) Core I-V model—drain current as function of Vgs, Vds, Vbs; (2) Capacitance model—gate, overlap, junction capacitances; (3) Noise model—1/f (flicker) and thermal noise; (4) Parasitic model—series resistance, junction diodes; (5) Reliability model—aging effects (NBTI, HCI). Model parameters: hundreds of parameters per device type, extracted by foundry from silicon measurements across process corners. Parameter extraction: measure I-V, C-V, noise on test structures → optimize model parameters to fit data → validate on independent circuits. Process corners: model files for typical (TT), fast-fast (FF), slow-slow (SS), fast-slow (FS), slow-fast (SF) representing process variability extremes. Statistical models: Monte Carlo parameters for mismatch (local variation) and process variation (global). PDK delivery: foundry provides compact models as part of process design kit with schematic symbols, layout cells, and DRC/LVS rules. Accuracy requirements: <5% error on key metrics (Idsat, Vth, gm, Cgg) for reliable circuit design predictions.