Contact Formation
Contact formation creates the vertical metal plugs that connect the first interconnect metal layer down to a transistor's source, drain, and gate terminals — the literal physical handoff between the front-end-of-line world of transistors and the back-end-of-line world of wiring, and a step where alignment accuracy and resistance control both matter enormously because the contact sits at the single narrowest, most electrically consequential point in the entire interconnect stack. Getting this handoff wrong in either dimension — misaligned or too resistive — directly degrades every transistor it touches, which is exactly why contact formation gets treated as its own specialized process module rather than as a minor step bridging two bigger ones.
The six-step sequence — depositing interlayer dielectric over the finished transistors, planarizing it with CMP, etching the actual contact hole, depositing a titanium nitride barrier layer, filling with tungsten via CVD, then CMP again to remove excess tungsten — exists as a coordinated whole because each step solves a specific problem the previous step either created or left unaddressed. Planarization after ILD deposition gives the subsequent lithography a flat surface to pattern accurately; the barrier layer specifically prevents tungsten from diffusing into and contaminating the surrounding dielectric and silicon; the final CMP removes tungsten that inevitably overflows the contact hole during CVD fill, leaving clean, isolated contact plugs behind — remove any single step from this sequence and the whole contact formation process breaks down somewhere downstream.
Aspect ratio at advanced nodes, commonly reaching roughly 10:1 for contact holes, makes void-free fill a genuinely difficult materials-engineering problem, because a deep, narrow hole can pinch off near its top before the deposition process has fully filled its bottom, trapping a void inside the finished contact plug. This void-fill challenge is exactly why chemical vapor deposition, rather than simpler physical deposition techniques, became the standard tungsten-fill method for contacts — CVD's superior conformal step coverage is specifically what lets it fill a deep, narrow hole from the bottom up rather than pinching closed prematurely the way a less conformal deposition technique would.
Contact resistance rises at every successive technology node specifically because contact area shrinks along with every other dimension, and resistance through a contact scales inversely with its cross-sectional area — meaning the same basic contact structure becomes measurably more resistive purely as a consequence of ordinary dimensional scaling, independent of any change in the contact material itself. This rising-resistance trend is exactly why tungsten, despite being the long-standing contact-fill standard, is increasingly being supplemented or replaced by cobalt or ruthenium at the most advanced nodes — these alternative metals offer genuinely lower resistivity at the very small contact dimensions where tungsten's resistance scaling becomes a real performance liability.
Self-aligned contact technology addresses the alignment challenge directly by exploiting etch selectivity between a dedicated contact etch-stop layer — typically a silicon nitride cap sitting on top of the gate — and the surrounding interlayer dielectric, which lets the contact etch overlap the gate's position without creating a short, since the nitride cap simply isn't removed by an etch chemistry tuned to remove the surrounding oxide instead. This selectivity-based protection is exactly what makes self-aligned contact essential at advanced nodes, where achievable lithographic overlay accuracy alone can no longer reliably guarantee the tight gate-to-contact spacing modern transistor density requires — SAC converts what would otherwise be an overlay-accuracy problem into an etch-chemistry-selectivity problem, which is a problem process engineering can solve far more reliably at these dimensions.
Middle-of-line (MOL) is the modern naming convention specifically covering the contact and local interconnect layers sitting between front-end-of-line transistor formation and back-end-of-line global wiring, and this naming reflects exactly how distinct contact formation's own specific challenges — aspect ratio, alignment, resistance scaling — have become relative to either the transistor formation or the wiring formation happening immediately on either side of it. This dedicated MOL terminology is precisely why contact formation gets organized, staffed, and optimized as its own specialized process module in modern fabs rather than being treated as a minor transitional step — the challenges genuinely specific to this handoff layer warrant dedicated engineering attention distinct from either neighboring process domain.