Contact over Active Gate
Contact Over Active Gate (COAG) is the design technique that allows the gate contact to be placed directly over the transistor channel (active region) — eliminating the need for gate contact extensions into inactive areas and enabling significant standard cell height reduction at advanced FinFET and GAA nodes.
Traditional vs. COAG
Traditional (COAG-prohibited):
- Gate contact must land on a gate extension that protrudes beyond the active fin region.
- This extension consumes ~1-2 fin pitches of horizontal space.
- Standard cell height must accommodate both P/N active regions AND gate contact extensions.
COAG (Contact Over Active Gate):
- Gate contact lands directly on the gate electrode over the active channel.
- No gate extension needed — entire cell width used for active transistors.
- Saves 1-2 fin pitches → enables shrinking cell height from 7-8 tracks to 5-6 tracks.
COAG Process Requirements
- Dielectric isolation: A self-aligned dielectric cap separates the gate contact from the adjacent source/drain contacts.
- Precise etch selectivity: Gate contact etch must stop on the cap over S/D and land only on the gate metal.
- Overlay tolerance: Contact-to-gate alignment within ~2 nm to avoid shorting to S/D.
Cell Height Impact
| Technology | Without COAG | With COAG | Savings |
|---|---|---|---|
| 7nm-class | 7.5T (track) | 6.5T | ~13% |
| 5nm-class | 6.5T | 5.5T | ~15% |
| 3nm-class | 6T | 5T | ~17% |
| 2nm-class | 5.5T | 4.5T | ~18% |
- Each track reduction = ~7-10% logic density improvement.
COAG in Production
- Intel 10nm (Intel 7): Early COAG implementation.
- TSMC N5/N3: Adopted COAG for cell height reduction.
- Samsung 3nm GAA: COAG mandatory for 5-track cells.
Design Implications
- EDA support: Place-and-route tools must handle new design rules for contact-over-active.
- DFM constraints: Contact placement over thin gate oxide requires defect-free dielectric caps.
- Power advantage: Shorter cells → shorter internal wires → lower RC → faster and lower power.
COAG is one of the most impactful density-enabling techniques in CMOS scaling — by placing gate contacts directly over the channel, it unlocks cell height reductions that compound into 15-20% logic density improvements at each node, equivalent to nearly a half-node shrink.