Cross-Section Preparation
Cross-section preparation is the technique of cutting through a semiconductor device perpendicular to the wafer surface to expose its internal layer structure for microscopic examination — the essential failure analysis and process development method that reveals everything hidden beneath the surface: transistor profiles, interconnect structures, void defects, contamination, and layer interfaces.
What Is Cross-Section Preparation?
- Definition: The process of cutting, polishing, or milling through a semiconductor specimen to expose an internal plane for examination by SEM, TEM, or optical microscopy — revealing the vertical (depth) structure that cannot be seen from top-down imaging.
- Purpose: Semiconductor devices are built in layers — cross-sectioning is the only way to directly observe and measure the vertical dimensions, interfaces, conformality, and defects within those layers.
- Methods: FIB milling (most common for site-specific), mechanical polishing, cleaving, and ion milling — each with different trade-offs of precision, speed, and quality.
Why Cross-Section Preparation Matters
- Layer Structure Verification: Directly measures film thicknesses, etch depths, trench profiles, and via dimensions — validating process targets.
- Defect Investigation: Reveals buried defects (voids in metal fills, delamination at interfaces, contamination particles trapped between layers) invisible from the surface.
- Profile Analysis: Shows sidewall angles, undercuts, and conformality of deposited and etched features — critical for process optimization.
- Failure Analysis Root Cause: Most semiconductor failures involve buried structural anomalies — cross-sectioning exposes the physical failure mechanism.
Cross-Section Methods
| Method | Precision | Speed | Best For |
|---|---|---|---|
| FIB | nm-level site targeting | 1-4 hours | Specific defects, TEM prep |
| Mechanical polish | µm targeting | 2-8 hours | Large-area overview |
| Cleave | ~100 µm targeting | Minutes | Quick look, crystalline materials |
| Broad ion beam | µm targeting, damage-free | 1-4 hours | Artifact-free surfaces |
| Plasma FIB | µm targeting, fast | 30-90 min | Large volume removal |
FIB Cross-Section Process
- Navigate: Use SEM with CAD overlay or defect map to locate specific target.
- Protect: Deposit Pt/C strap over the area to prevent rounding and damage.
- Rough Mill: High-current FIB removes bulk material to create viewing trench.
- Fine Polish: Low-current FIB creates artifact-free cross-section face.
- Image: SEM captures high-resolution images of exposed cross-section.
Common Cross-Section Artifacts
- Curtaining: Vertical striping from differential milling rates between materials.
- Redeposition: Milled material depositing on cross-section face — obscures features.
- Amorphization: FIB damage creates amorphous surface layer — reduces HRTEM quality.
- Rounding: Edge rounding at surface without protective cap — distorts profile measurements.
Cross-section preparation is the window into the hidden world of semiconductor device structure — providing the direct visual evidence that process engineers, failure analysts, and materials scientists need to understand, optimize, and debug the complex multilayer structures that comprise modern integrated circuits.