Cu-Cu Bonding

Copper-to-copper direct bonding joins two metal surfaces into a single continuous conductor without solder, adhesive or any intermediate phase. In advanced packaging it appears as the metal half of hybrid bonding, where copper pads and the surrounding dielectric bond simultaneously, and it is the mechanism that takes die-to-die interconnect pitch below what solder can physically support.

Pad pitch scaling

A solder joint has a minimum volume below which the brittle intermetallic formed on reflow consumes the joint and bridging risk becomes uncontrollable; that floor sits near 40 μm. Direct bonding has no solder, so pitch is limited by lithographic overlay instead of metallurgy. Production pitches sit between 3 and 10 μm, with sub-micron demonstrated.

The payoff is quadratic, because interconnect density is an areal quantity:

$$ \rho_{\text{IO}} = \frac{1}{p^{2}} $$

Going from a 40 μm micro-bump to a 4 μm bond pad is a hundred-fold increase in available connections per unit area, not a ten-fold one. That is what pays for interfaces like HBM4's 2048-bit bus and for 3D-stacked logic where a cache die must present thousands of connections to the core beneath it.

CMP dishing is the process-limiting step

Bonding proceeds dielectric-first at room temperature, and the copper must sit slightly *below* the dielectric plane so the two oxide or SiCN surfaces can make intimate contact before the metal does. That recess — typically 2 to 10 nm — is produced by the dishing that copper CMP naturally causes, and it must be controlled to within a few nanometres across a 300 mm wafer.

Material removal follows Preston's relation, with removal rate proportional to pressure and relative velocity,

$$ MRR = k_p \cdot P \cdot V $$

but dishing is a differential effect: copper polishes faster than the surrounding dielectric, and the disparity grows with pad width and falls with pattern density. To first order

$$ \delta_{\text{dish}} \propto k_p P V t \cdot f\!\left(w_{\text{pad}},\, \rho_{\text{pattern}}\right) $$

so a wide pad in a sparse region dishes far more than a narrow pad in a dense array. Uniform dummy-pad fill to equalise pattern density is therefore mandatory, exactly as it is for damascene copper wiring, and the recess specification is as much a layout constraint as a process one.

The window is unforgiving in both directions. Too little recess and the copper contacts before the dielectric, holding the bonding surfaces apart and leaving a dielectric void that propagates as a delamination front. Too much recess and thermal expansion during anneal cannot close the gap, leaving an open circuit that no amount of subsequent processing recovers.

Cu-Cu Direct Bonding: Dishing Sets the Recess, Anneal Closes It recess 2–10 nm — a CMP dishing control problem CMP dishing depends on pad width and density narrow: shallow wide: deep dish MRR = k_p · P · V Cu removes faster than dielectric dummy fill equalises pattern density The recess window too little → dielectric void 2–10 nm → continuous Cu too much → open circuit Δh = α_Cu · h_Cu · ΔT at 250–350 °C grain-boundary diffusion erases the interface — joint becomes bulk Cu

Thermal anneal and grain coalescence

Closure happens in two stages. First the pads expand thermally across the recess,

$$ \Delta h = \alpha_{\text{Cu}}\, h_{\text{Cu}}\, \Delta T $$

bringing the surfaces into physical contact. With copper's expansion coefficient near 17 ppm/K, a pad a few hundred nanometres thick closes a several-nanometre gap over a 250 to 350 °C excursion — which is why the recess specification and the anneal recipe are designed together rather than independently.

Second, and more importantly, the contacting surfaces interdiffuse. Grain boundaries sweep across the original interface, grains grow through it, and the joint becomes metallurgically continuous copper. Driving force is the reduction in surface and interface energy, and kinetics are governed by grain-boundary diffusion, which is why the anneal is held for tens of minutes rather than seconds. A properly annealed bond shows no detectable interface in cross-section.

Cu–Cu Bond Formation — From Recessed Pads to a Shared Grain Network dielectric contact comes first; heat and surface diffusion close the gap; grain growth strengthens the metal path 1 · after CMP controlled recess + smooth dielectric native CuO must be removed 2 · dielectric-first contact dielectric bonded; Cu gap remains particle here creates a much larger void 3 · low-temperature anneal surface diffusion closes microvoids grains grow across the original plane two closure mechanisms share the work larger pads thermal expansion and stress-driven bulge-out smaller pads surface diffusion and local morphology dominate therefore recess, pad size, surface chemistry, temperature, and dwell time must be co-designed A good bond is not two pads merely touching—it is a low-void metallic path whose microstructure survives current and moisture. The original interface can become difficult to see, but reliability still depends on Cu migration, dielectric integrity, and edge sealing.
Anneal Kinetics — Temperature Buys Diffusion Exponentially schematic closure curves from Arrhenius surface diffusion; exact times depend on pad geometry and surface state 00.25×0.5×0.75×1× dwell 0%25%50%75%100% normalized anneal time → bonded Cu area / void closure → lower temperature: slow closure mid-temperature process window higher temperature: rapid closure surface diffusion coefficient Ds = D₀ exp(−Es / kBT) temperature accelerates closure—but also spends BEOL thermal budget the optimum is not “hottest” high T speeds diffusion and grain growth but increases stress, Cu motion, and low-k risk surface preparation lowers the temperature needed The toll bridge is a wide low-temperature process window: clean Cu, correct recess, strong dielectric bond, and low void density.

Surface diffusion, not expansion alone

Thermal expansion helps bring recessed pads together, but it is not the whole closure mechanism. Surface diffusion smooths the copper profile and transports material into uncontacted regions with Arrhenius kinetics,

$$ D_s = D_{s0}\exp\!\left(-\frac{E_s}{k_B T}\right) $$

Recent modeling verified against cross-sectional microscopy indicates that expansion contributes strongly for larger features, while surface diffusion becomes dominant for smaller pads. As pitch shrinks, native-oxide removal, plasma chemistry, surface composition and post-CMP morphology therefore matter more—not less.

The reliability boundary

Removing solder eliminates solder fatigue and intermetallic growth, but it does not eliminate interface reliability. Moisture can enter exposed die edges, weaken the dielectric bond, create voids and raise pad resistance. Under extreme current and temperature stress, Cu migration, local burnout and dielectric breakdown remain possible. The moat is consequently a qualified process window—CMP planarity, activation, queue time, placement cleanliness, anneal and edge sealing—not copper as a commodity.

References

  • IEEE ECTC, “Modeling of Copper Hybrid Bonding Anneal” (2024).
  • IEEE ECTC, “Integration Solution for Thin D2W Hybrid Bonding for Yield and Reliability” (2025).
  • IEEE Transactions on Semiconductor Manufacturing, “Critical Roles of Copper Surface Planarity in Achieving Reliable Cu/SiO₂ Hybrid Bonding” (2026).
  • IBM Research, “Exploring Cu–Cu Hybrid Bonding Failure Mechanisms under Current Stress via 3D Focused Ion Beam Tomography” (ECTC 2026).

That continuity is the durable advantage over solder. There is no intermetallic to embrittle, no solder to fatigue, no underfill needed to redistribute strain. Current-carrying capability can rise substantially because solder and its intermetallic phases are absent. Grain growth can reduce the electrical signature of the original plane, but the bonded region is not immune to electromigration, moisture-assisted voiding or dielectric breakdown. The trade is process severity: sub-nanometre surface roughness, nanometre-scale recess control, and near-absolute particle cleanliness, since one particle voids an area thousands of times its own diameter.

Surface activation

Room-temperature bond initiation requires surfaces that are both atomically clean and chemically receptive. Copper oxidises immediately on air exposure, and copper oxide does not bond. Production flows therefore use plasma activation — typically nitrogen or a reducing chemistry — immediately before contact, combined with tightly controlled queue times between activation and bonding. The dielectric is activated in the same step, which is part of why SiCN has displaced plain oxide: it holds activation longer and reaches higher bond energy at the modest temperatures the copper anneal allows.

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