Cu Cu Hybrid Bonding

Hybrid bonding joins two wafers or dies by bonding copper pads and the surrounding dielectric at the same time, producing a metallurgical copper-to-copper connection with no solder, no underfill and no gap. Commercialised as direct bond interconnect (DBI), it is the interconnect that takes die-to-die pitch below the floor solder can reach.

Why solder stops

A micro-bump is a solder joint, and solder joints have a minimum viable volume. As pitch shrinks the joint must shrink, but the intermetallic compound that forms with the copper pad on reflow has a nearly fixed thickness, so it consumes a growing fraction of a shrinking joint until the connection is essentially all brittle IMC. Bridging risk rises at the same time, because molten solder must be confined to a shrinking footprint. The practical floor sits near 40 μm, with heroic processes reaching the mid-20s.

Hybrid bonding removes solder from the problem entirely, and pitch is then limited by lithographic overlay rather than metallurgy. Demonstrated pitches are below 1 μm; production is in the 3 to 10 μm range. Since interconnect density scales as $1/p^{2}$, this is a two-to-three order of magnitude increase in available connections.

The three surface requirements

The process succeeds or fails on surface preparation, and all three requirements are severe.

*Planarity.* The dielectric surfaces must contact intimately across the whole wafer, so CMP must deliver roughness well under a nanometre — the working specification is

$$ \sigma_{\text{RMS}} < 0.5\ \text{nm} $$

across a 300 mm wafer. There is no reflow to accommodate topography; a surface that is not flat simply does not bond.

*Copper recess.* The copper pads must sit slightly below the dielectric plane, typically 2 to 10 nm, because bonding proceeds dielectric-first at room temperature and the copper is brought into contact afterwards by thermal expansion. Too little recess and copper contacts first, holding the dielectric surfaces apart and leaving voids. Too much and the copper cannot close the gap during anneal, leaving an open. The recess window is a CMP dishing control problem, and dishing depth in a damascene pad follows the Preston relation modified by pattern density,

$$ \delta_{\text{dish}} \propto k_p P V t \cdot f(\rho_{\text{pattern}}, w_{\text{pad}}) $$

so wide pads and low-density regions dish more. Dummy pad fill to equalise pattern density is therefore mandatory, exactly as it is for damascene copper.

*Cleanliness.* A single particle holds the surfaces apart over an area thousands of times its own diameter, producing a void that fails every connection inside it.

Hybrid Bonding: Dielectric First, Copper on Anneal SiCN/SiO₂ bonds at room temperature — Cu closes the recess at 250–350 °C 1. Contact Cu recessed 2–10 nm — gap remains 2. Dielectric bond Si–O–Si / Si–N covalent bonds form 3. Anneal Cu expands, closes gap, grains coalesce The recess window is narrow in both directions too little recess Cu touches first → dielectric void too much recess gap survives anneal → open circuit 2–10 nm CMP σ_RMS < 0.5 nm across 300 mm — no reflow exists to absorb topography pitch p → ρ_IO ∝ 1/p²

Bonding chemistry: SiO₂ and SiCN

Room-temperature bonding proceeds through hydrogen-bonded surface species that convert to covalent bonds on anneal. For silicon dioxide the condensation reaction is

$$ \mathrm{Si\!-\!OH} + \mathrm{HO\!-\!Si} \;\longrightarrow\; \mathrm{Si\!-\!O\!-\!Si} + \mathrm{H_2O} $$

and the water produced must diffuse away through the bond interface; trapped water is a classic void source. Silicon carbonitride has largely displaced plain oxide as the bonding dielectric because it reaches higher bond energy at lower anneal temperature, tolerates the copper recess process better, and simultaneously serves as a copper diffusion barrier — which plain oxide does not.

Copper closure during anneal is a combination of thermal expansion across the recess and grain-boundary diffusion across the now-contacting interface:

$$ \Delta h = \alpha_{\text{Cu}}\, h_{\text{Cu}}\, \Delta T $$

At 250 to 350 °C the pads expand into contact, then interdiffuse until the original interface disappears into a continuous grain structure. The finished joint is metallurgically indistinguishable from bulk copper, which is why hybrid-bonded interconnect carries far higher current density than a solder joint and exhibits essentially no electromigration at the interface.

Micro-bumpHybrid bond (DBI)
Pitch floor~40 µm&lt;1 µm demonstrated
Joint materialsolder + IMCcontinuous Cu
Underfillrequirednone
Electrical parasiticsbump L and Cnear-zero
Thermal pathsolder, poordirect Cu, excellent
Process sensitivityreflow profileCMP, recess, particles

Wafer-to-wafer versus die-to-wafer

W2W bonds two full wafers and achieves the finest pitch, because whole-wafer alignment is a lithographic problem. Its weakness is yield: dies are paired blind, so a good die can be bonded to a bad one, and compound yield falls as the product of the two. D2W places known-good dies onto a carrier wafer, preserving yield at the cost of coarser alignment and much lower throughput. The choice is economic — W2W suits high-yield, identical-die stacking such as memory; D2W suits expensive heterogeneous dies where discarding a good compute die is unacceptable.

HBM4 is exactly the identical-die, high-yield case this trade-off was describing. Every DRAM die in an HBM stack is the same part, so W2W hybrid bonding is the natural fit, and HBM4 is the generation where it displaces micro-bumps as the primary die-to-die interconnect inside the stack rather than appearing only at the package level.

Why HBM4 Trades Micro-Bumps for Hybrid Bonding Inside the Stack the same die-to-die joint now has to carry both more signal density and the base die's heat HBM3E — micro-bump stack ~40 µm bump pitch, solder + underfill gap heat crosses a poor, resistive gap HBM4 — hybrid-bonded stack sub-10 µm pitch, continuous Cu, no gap heat crosses direct metal, almost no resistance the same bond that tightens signal pitch also lowers the base die's R_thermal a tighter, denser bond grid gives each die more landing pads for the wider TSV field this generation's interface needs, while removing the worst link in the base die's heat path two separate HBM4 problems, one process change fixing both at once bump pitch and TSV keep-out zone are still two different constraints — hybrid bonding fixes the first without touching the second, which is why both still have to be engineered separately

That pairing — tighter interconnect density and a better thermal path, from the same process change — is not a coincidence, and it is also not the whole story. Hybrid bonding fixes the bump-to-bump pitch limit; it does nothing to the TSV's own keep-out zone, which is a separate stress-field problem rooted in the via itself, not in how dies are joined. HBM4 needs both fixes at once — a denser bond grid to land more connections, and careful TSV layout to keep each via's exclusion radius from eating the array — and getting one without the other would still leave the stack bottlenecked.

Read HBM4 hybrid bonding through a *which-constraint-does-this-actually-fix* lens rather than a *"better bonding is just better"* lens: $1/p^2$ interconnect density and a near-zero thermal resistance path both come from retiring the ~40 μm solder floor, but the $A_{KOZ}=\pi(r_{KOZ}^2-a^2)$ tax on every TSV survives completely untouched by this change — which is exactly why this series has needed a separate article for each of the base die, the TSV field, and now the bond between them.

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