Dark Silicon

Dark silicon is the fraction of a chip that must be left unpowered — kept dark — at any given moment because the whole die cannot be switched on within its power and thermal budget. Modern nodes can pack far more transistors onto a die than the chip is allowed to energize simultaneously, so a growing share of the silicon sits idle at any instant. The transistors are physically there; the power budget, not the area, is what limits how many can run at once.

It is the direct consequence of Dennard scaling ending. For decades Dennard scaling let supply voltage fall as transistors shrank, so power per unit area stayed roughly constant even as density doubled each node. Around the mid-2000s that broke: voltage could no longer scale down proportionally, so each new node crams more transistors into the same area without a matching drop in power-per-transistor. Density kept rising; power density rose with it. The chip's fixed thermal envelope then caps how much can be active, and the surplus becomes dark silicon.

The dark fraction grows with every node. Because transistor count per area climbs faster than the power budget, the share of the die you can light up at full speed shrinks generation over generation — estimates put it from a modest fraction at older nodes toward the majority of the die at the leading edge. This is why simply adding more identical cores stopped translating into proportional performance: you cannot power them all at once, so throughput is bounded by heat and current delivery, not by how many cores you printed.

Dennard eraPost-Dennard (dark silicon)
Voltage vs shrinkscales down~flat
Power / mm²~constantrises each node
Limit on active areaarea / countpower & thermal budget
More cores →more usable throughputmany must idle
Design responsescale frequencyspecialize, gate, dim
Dark silicon — you can fit the transistors, but not power them all at once More transistors per node, smaller share you can switch 7 nm-class~55% dark5 nm-class~70% dark3 nm-class~80% dark lit = simultaneously powered · dark = must stay idle within the power budget Why: power density stopped falling 1×2×4×6×8×newer node →power / mm²Dennard endsideal (Dennard)actual Dennard scaling once kept power-per-mm² flat as transistors shrank; when it ended (~2005), voltage stopped dropping with size. Now each node packs more transistors into the same area than a fixed power & thermal budget can switch — the surplus must go dark. Responses: dim/gate unused blocks, specialized accelerators (use area only when needed), multi-Vdd domains, DVFS, better cooling.

The design answer is specialization and gating, not more uniform cores. If most of the die must stay dark, the winning move is to fill that area with blocks that are only powered when their specific job runs — dedicated accelerators, fixed-function engines, extra cache — plus aggressive power gating, clock gating, multi-voltage domains, and dynamic voltage/frequency scaling to keep active power under the cap. Dark silicon reframes area as cheap and power as the scarce resource: you spend transistors to build many specialized units and light up only the few you need for the workload at hand.

Read dark silicon through a quant lens rather than a 'wasted area' lens: the binding budget is watts and junction temperature, not square millimeters, so the number that matters is the fraction of the die you can energize within the thermal envelope — and that fraction falls each node as density outruns Dennard-limited power. The design question becomes performance-per-watt within a fixed power cap: which specialized blocks earn their area by delivering the most useful work per joule when lit, since everything else has to stay dark anyway.

Dark Silicon — The Power Wall transistor count grows with Moore's Law, but not all can be powered on simultaneously — the utilization wall The Dark Silicon Problem CPU cores GPU NPU dark dark (powered off) ~50-80% of transistors idle at any time Why: Dennard scaling ended (~2006) Before: shrink transistor → same power density (voltage scales) After: shrink transistor → voltage stuck (~0.7V) → power density rises Result: more transistors, but can't turn them all on (thermal limit) Solutions to Dark Silicon Heterogeneous computing specialized accelerators (GPU, NPU, DSP, ISP) DVFS (dynamic voltage/freq) scale power to workload demand Power gating shut off unused blocks completely (MTCMOS) Chiplets only power the chiplets you need for the task Power Density Timeline Pentium 4 (2004): 100 W/cm² (sun surface!) Modern GPU (2024): 1 W/mm² average Hotspots: 5-10 W/mm² peak (ALU clusters) Thermal limit: ~100-150W per cm² removable H100: 700W total ÷ 8.14 cm² = 86 W/cm² avg But hotspots hit 300-500 W/cm² locally How Industry Adapts Apple M-series big.LITTLE + NPU + GPU power-gate idle blocks NVIDIA H100 SM scheduling + clock domain power gating AMD chiplets per-CCD power states activate on demand Near-threshold ~0.5V operation (research) 10× energy efficiency Dark silicon is why specialization won: general-purpose cores waste power, so we build NPUs, TPUs, and accelerators instead. We can build more transistors than we can power — the era of "more cores = more speed" ended with Dennard scaling.

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