Defect Inspection

Metrology and inspection are the two measurement disciplines that keep a semiconductor fab in control — they are how a foundry knows, wafer by wafer, whether hundreds of process steps are producing the right structures and whether anything has gone wrong. The two answer different questions. Metrology measures dimensions and material properties: is the feature the right size, is the film the right thickness, are the layers aligned? Inspection hunts for defects: is there a particle, a bridge, a missing pattern, a scratch? Together they generate the data that feeds statistical process control and the feedback loops that hold yield, and they are the core business of companies like KLA, alongside Applied Materials, Hitachi High-Tech, and ASML.

Metrology measures — CD, film thickness, profile, and overlay — non-destructively and in-line. The central number is critical dimension (CD): the width of the smallest features, measured either by a CD-SEM (a scanning electron microscope tuned for linewidth) or by optical scatterometry / OCD, which fits the diffraction from a periodic grating to a physical model to extract CD, height, and sidewall angle at high throughput. Film thickness and optical properties come from ellipsometry and X-ray reflectometry; layer registration comes from overlay metrology on scribe-line targets. Because these tools run on production wafers between process steps, they must be fast and non-destructive — trading some absolute accuracy for the throughput needed to sample every lot without slowing the line.

Inspection finds defects, trading throughput against sensitivity. Inspection tools scan the wafer and flag anything that should not be there, usually by comparing supposedly identical dies (or repeating cells) and treating any difference as a candidate defect. Optical inspection is fast and covers whole wafers — brightfield for many defect types, darkfield for scattering particles — but its resolution is limited by the wavelength of light. Electron-beam inspection can provide finer sampling and voltage-contrast sensitivity to some electrical faults, but interaction depth, charging, material contrast, landing energy, and throughput constrain which defects it can see. It is therefore used selectively on difficult layers and for root-cause work. Flagged defects are then passed to a review SEM that images and classifies each one, separating true yield-killers from harmless nuisance defects.

Defect counts obey Poisson statistics, and yield follows. If killer defects land randomly with density $D_0$ per unit area, the number on a chip of area $A$ is Poisson-distributed and the probability of zero killers — the yield — is

so a $100\:\mathrm{mm^2}$ die at $D_0 = 0.1\:\mathrm{cm^{-2}}$ yields $Y \approx e^{-0.1} \approx 0.90$. Every defect-learning cycle is an attempt to drive $D_0$ down: inspection finds candidates, review SEM separates killers from nuisances, and Pareto analysis points the fix at the process step generating them.

The threshold must be optimized against downstream cost, not image beauty. Lowering $\tau$ raises probability of detection but floods review SEM capacity with nuisance candidates; raising it protects throughput but lets more killer defects escape. The relevant operating point minimizes expected loss,

subject to the wafer-area throughput the layer can afford. Because $C_{\mathrm{escape}}$ changes dramatically by layer and defect class, one universal threshold is not rational.

This classifier-and-review loop is the economic moat. Optical inspection supplies coverage, e-beam supplies sensitivity, review supplies labels, and fab genealogy converts a coordinate into a root cause. The value comes from learning which signals predict yield loss and feeding that knowledge back into recipes—not from maximizing raw candidate count.

The signal chain exposes why nominal resolution alone does not determine inspection performance. Collection geometry changes which spatial frequencies and scattering angles reach the detector; alignment and reference choice determine how much repeating pattern cancels; thresholding converts the residual into candidates; and review converts a sampled subset into physical classes and process actions. A recipe is useful when the whole chain finds the defect classes that matter at sustainable wafer and review throughput.

Both feed process control, closing the loop that protects yield. The measurements don't merely grade wafers; they drive control. Statistical process control (SPC) charts each parameter against control limits so that drift or an out-of-spec excursion triggers a hold before bad wafers pile up, and advanced process control (APC) feeds metrology results back to tune the next run's litho dose, etch time, or deposition. This is why sampling strategy matters: measure too little and defects escape, measure too much and throughput and cost suffer, so fabs carefully optimize where and how often to look. As features shrink, inspection increasingly combines improved optical channels, selective e-beam sampling, specialized actinic methods where EUV-mask physics requires them, and model-assisted candidate ranking and classification.

Read metrology and inspection through a quant lens rather than a 'check the wafer' lens: they convert the physical wafer into two streams of numbers — a distribution of dimensions (CD, thickness, overlay) and a catalog of defects — and everything downstream is statistics on those streams. Metrology's game is an inverse problem: infer a structure's true profile from an indirect signal (electrons, diffracted light) fast enough to sample production. Inspection's game is a detection problem: maximize the probability of catching a real killer defect while holding false alarms and scan time down. Yield learning depends on holding the first distribution tightly and detecting the second with enough sensitivity, coverage, and sampling frequency to expose actionable excursions. The optimum inspection budget is layer- and risk-dependent; complete enumeration is neither technically possible nor economically necessary.