Delay Fault

Delay Fault is a defect model where a signal arrives at its destination later than expected — caused by resistive opens, weak transistors, or process variations that slow down signal propagation, leading to timing violations.

What Is a Delay Fault?

• Physical Cause: Resistive vias, thin metal lines, gate oxide thickness variation, transistor degradation.
• Effect: The logic value is eventually correct, but it arrives *too late* (after the clock edge).
• Models:
• Transition Fault: Tests a single gate's speed (simplified).
• Path Delay Fault: Tests the cumulative delay of an entire critical path (comprehensive).

Why It Matters

• Modern Scaling: As feature sizes shrink, process variation causes more delay faults than stuck-at faults.
• At-Speed Required: Delay faults are invisible at slow test speeds. Only caught with at-speed testing.
• Reliability: Marginal delay faults worsen over time (aging, electromigration), causing field failures.

Delay Fault is the hidden killer of chip reliability — a timing bomb that ticks correctly at slow speeds but explodes under real-world operating conditions.