Depth of Focus (Dof)
Depth of focus (DOF) is the range of vertical wafer positions over which the projected image stays sharp enough to print features within spec — and it's locked in a direct trade-off against resolution through the same lens parameter, numerical aperture, that resolution itself depends on. Push NA higher to resolve smaller features, and DOF collapses far faster than resolution improves.
The math behind that trade-off is simple, but its consequence is brutal. The Rayleigh DOF relationship is DOF = k₂ × λ / NA² — note the squared NA in the denominator, versus resolution's single power of NA. Push NA from 0.93 to 1.35 (roughly a 45% increase) to gain that much resolution, and DOF doesn't just shrink by 45% — it shrinks by the square of that factor, over twice as fast. At 193nm immersion lithography's NA of 1.35, DOF works out to roughly 53nm: a focus window thinner than many of the physical variations the wafer itself introduces before the scanner even starts exposing.
That 53nm budget gets consumed by sources that have nothing to do with the scanner's own precision. Wafer non-flatness — local height variation across the exposure field — typically eats 20–40nm on its own for an advanced wafer. Topography left behind by underlying metal, dielectric, and gate layers can consume another 50–100nm or more, often exceeding the entire DOF budget by itself on a complex, multi-layer stack. Residual lens aberrations (field-dependent focal plane curvature, astigmatism) and environmental drift in air or immersion-fluid refractive index eat into what little margin remains. Add it up, and a process with 53nm of theoretical DOF can easily have negative *effective* DOF before any pattern is even exposed — which is precisely why so much fab engineering outside the scanner itself exists purely to protect focus margin.
Chemical-mechanical planarization (CMP) is, from this angle, a lithography-enabling step as much as a polishing one. Flattening wafer topography between layers directly returns DOF budget that topography would otherwise consume — a planarization process isn't just making the wafer prettier, it's buying back focus margin the next lithography layer desperately needs. Phase-shift masks and sub-resolution assist features (SRAF) attack the same problem from the optics side, improving image contrast so a slightly defocused exposure still prints acceptably instead of failing outright. Source optimization and full computational lithography co-optimize illumination, mask, and resist together, searching for the combination that maximizes usable DOF for a specific pattern rather than treating resolution and focus margin as separately solved problems.
This is why High-NA EUV's jump from 0.33 to 0.55 NA is a genuine engineering gamble, not just a resolution upgrade. The same squared relationship applies: a 67% NA increase doesn't just demand a correspondingly tighter DOF budget — it demands one nearly three times tighter, at exactly the moment EUV already has famously little margin to spare. Every resolution gain in lithography's history has come paired with exactly this cost, which is why process-window engineering, not scanner specification alone, decides whether a resolution number is actually manufacturable.