Die
A die is a single rectangular piece of a processed semiconductor wafer containing one complete integrated circuit — the chip itself, before it's ever packaged. After hundreds of fabrication steps turn a blank wafer into a grid of identical finished circuits, the wafer is sliced along its scribe lines to separate each die into an individual, independently usable (or discardable) unit.
The same two random defects do wildly different damage depending on die size. Scattered randomly across the wafer, those defects land on roughly the same physical area either way — but a small die only occupies a tiny fraction of the wafer, so a defect is unlikely to hit any particular die, and even when it does, only one small chip is lost. A large die occupies a much bigger fraction of the same wafer, so the same defect is far more likely to land inside *some* die's boundary — and because each die is worth so much more silicon, losing it wastes proportionally more of the wafer. This is the direct mechanical reason multi-die chiplet designs have become so popular: splitting one large design into several smaller interconnected die can dramatically improve yield economics, even after accounting for the packaging complexity of stitching them back together.
The core yield math is straightforward, even if the economics it drives are not.
| Metric | Formula | Typical value |
|---|---|---|
| Gross die per wafer | π × (r − edge exclusion)² / die area | 100–5,000+ |
| Die yield | good die ÷ gross die × 100% | 70–95% |
| Wafer yield | good wafers ÷ total wafers × 100% | 95–99% |
| Defect density (D₀) | defects per cm² | 0.05–0.5 |
Run the cost consequence through directly: a $10,000 wafer yielding 500 good die costs $20 per die; if yield drops to 50% on the same wafer, the same $10,000 now only buys 250 good die, doubling cost per die to $40 — the wafer's processing cost didn't change at all, only how many usable chips came out of it.
Separating die is itself a precision manufacturing step, not an afterthought. Diamond blade dicing — a thin blade spinning at 30,000–60,000 RPM — remains the fast, economical default. Laser dicing reduces mechanical stress for thin wafers and fragile low-k dielectrics. Stealth dicing creates an internal modification layer with a laser, then cleaves the wafer along it for essentially zero kerf loss. Plasma dicing etches through the scribe lines entirely, the only method that handles irregular die shapes and sub-100µm wafers cleanly. Choice of method is itself a yield lever — a dicing process that chips or cracks die at the edge destroys exactly the good silicon the rest of the fab spent months creating.