Die to Die Interconnect D2d

Die-to-Die (D2D) Interconnect Design is the physical and protocol layer engineering that enables high-bandwidth, low-latency, and energy-efficient communication between chiplets within a multi-die package — where D2D links must achieve 10-100× higher bandwidth density and 10-50× lower energy per bit than off-package SerDes, operating at 2-16 Gbps per wire over distances of 1-25 mm with bump pitches of 25-55 μm that exploit the controlled, low-loss environment of the package substrate or silicon interposer.

D2D vs. Chip-to-Chip SerDes

Off-package SerDes (PCIe, Ethernet) drives signals over lossy PCB traces with connectors, requiring complex equalization (CTLE, DFE), CDR, and 112-224 Gbps per lane at 3-7 pJ/bit. D2D links operate within a package where channel loss is <3 dB, enabling:
- Simple signaling: single-ended or low-swing differential, no equalization needed.
- Source-synchronous clocking: forwarded clock eliminates CDR (saves power and area).
- Massively parallel: hundreds to thousands of wires at 25-55 μm pitch.
- Low energy: 0.1-0.5 pJ/bit (10-50× better than off-package SerDes).

UCIe (Universal Chiplet Interconnect Express)

The industry-standard D2D protocol (version 1.1):
- Standard Package: 25 Gbps/lane on organic substrate, bump pitch ≥ 100 μm. 16 data lanes per module. Bandwidth: 40 GB/s per module.
- Advanced Package: 32 Gbps/lane on silicon interposer/bridge, bump pitch 25-55 μm. 64 data lanes per module. Bandwidth: 256 GB/s per module.
- Protocol Options: Streaming (raw data, application-defined), PCIe (standard PCIe TLPs), CXL (cache-coherent memory sharing). Protocol layer is independent of PHY — any protocol runs on the same physical link.
- Retimer: Optional retimer for longer reach (>10 mm) or crossing interposer boundaries.

D2D PHY Architecture

• Transmitter: Voltage-mode driver with impedance matching. Swing: 200-400 mV (vs. 800-1000 mV for off-package). Low swing reduces power and crosstalk.
• Receiver: Simple sense amplifier or clocked comparator. No equalization needed for <3 dB loss channels. Optional 1-tap DFE for higher-loss channels.
• Clocking: Forwarded clock with per-lane deskew. DLL or FIFO-based phase alignment between forwarded clock and local clock. Eliminates the complex CDR required in off-package SerDes.
• Redundancy: Spare lanes for yield recovery — if one bump in 100 is defective, the link training remaps traffic to spare lanes. Essential for high-pin-count hybrid bonding.

Bandwidth Density Comparison

Die-to-Die Interconnect Design is the packaging-aware circuit design that makes chiplet architectures perform like monolithic chips — achieving the bandwidth and latency between separate dies that approach what an on-die bus would provide, while consuming a fraction of the power of conventional off-package links.