Differential Signaling

Differential signaling transmits information as the voltage difference between two complementary signal lines (a positive and negative pair) rather than as a single-ended voltage relative to ground — providing superior noise immunity, reduced electromagnetic interference, and higher data rates.

How Differential Signaling Works

• Two Wires: Signals $V^+$ and $V^-$ carry the same information but with opposite polarity. When $V^+$ goes high, $V^-$ goes low, and vice versa.
• Differential Voltage: The receiver detects the difference: $V_{diff} = V^+ - V^-$. A positive differential = logic 1; negative = logic 0.
• Common-Mode Rejection: Noise that couples equally to both wires (ground bounce, EMI, crosstalk) appears on both $V^+$ and $V^-$ — the differential receiver subtracts it out.

Advantages Over Single-Ended Signaling

• Noise Immunity: Common-mode noise is rejected. Only noise that affects just one wire (or affects them differently) causes errors.
• Lower Voltage Swing: Because the receiver detects a difference, the voltage swing can be smaller (e.g., ±200mV instead of 0–1V) — faster transitions, less power.
• Reduced EMI: The two wires carry equal and opposite currents — their electromagnetic fields cancel at a distance, reducing emissions.
• Better Signal Integrity: Less sensitive to ground bounce and supply noise since the signal is not referenced to ground.
• Higher Data Rates: The combination of noise immunity, lower swing, and reduced EMI enables multi-GHz data transfer.

Common Differential Standards

• LVDS (Low-Voltage Differential Signaling): ±350mV swing, 100Ω impedance. Widely used for display, camera, and general-purpose high-speed links.
• CML (Current-Mode Logic): Used in high-speed SerDes (PCIe, USB, Ethernet). Very fast, DC-coupled.
• PECL/LVPECL: ECL-based differential — used in clock distribution and telecom.
• DDR (SSTL Differential): DDR memory uses differential strobes and some differential data.

Layout Considerations for Differential Pairs

• Length Matching: Both wires must have the identical length to maintain timing alignment. Length difference creates skew that degrades signal quality.
• Spacing: Consistent spacing between the $V^+$ and $V^-$ wires to maintain controlled differential impedance (typically 100Ω).
• Symmetry: The routing environment should be symmetric — both wires see the same parasitic coupling, same reference planes, same via structures.
• Guard Traces: Optional grounded guards on both sides of the pair for additional isolation.
• Avoid Splitting the Pair: Never route the two wires on different layers or around obstacles separately — they must travel together.

On-Chip Differential Signaling

• High-speed SerDes I/O on modern chips use on-die differential drivers and receivers.
• Clock distribution sometimes uses differential clocking for better jitter performance.
• Analog circuits (op-amps, ADCs) inherently use differential signal paths internally.

Differential signaling is the dominant technique for high-speed data transfer — virtually every interface running above 1 Gbps uses differential signaling for its superior noise performance.