Direct Tunneling

Direct Tunneling is the quantum mechanical transmission of carriers through the full width of a thin insulating barrier — occurring at low voltages in ultra-thin gate dielectrics below 3nm, it set the hard physical limit on SiO2 gate oxide scaling and forced the industry-wide transition to high-k metal gate stacks below the 65nm node.

What Is Direct Tunneling?

• Definition: Tunneling in which the carrier wavefunction penetrates across the complete thickness of the insulating layer from one electrode to the other without the triangular barrier narrowing characteristic of Fowler-Nordheim tunneling.
• Thickness Regime: Direct tunneling dominates when the oxide is thin enough (below approximately 3nm for SiO2) that the wavefunction amplitude at the far surface is non-negligible even at low electric fields.
• Voltage Independence: Unlike Fowler-Nordheim tunneling, direct tunneling current is relatively weakly dependent on applied voltage because the barrier shape changes little at the low fields of normal logic operation.
• Exponential Thickness Dependence: Direct tunneling current increases by approximately one order of magnitude for every 0.2nm reduction in SiO2 thickness — the steepest practical scaling wall in transistor history.

Why Direct Tunneling Matters

• SiO2 Scaling Limit: At the 90nm node, SiO2 gate oxides reached approximately 1.2nm (about 4 atomic layers) — below which direct tunneling gate leakage current density exceeded 1-10 A/cm2 at normal supply voltage, contributing hundreds of milliwatts per square centimeter of static power.
• High-K Motivation: Direct tunneling through physically thin SiO2 was the primary driver that motivated Intel, TSMC, Samsung, and the entire industry to develop HfO2-based high-k dielectrics, which provide the same gate capacitance from a physically thicker barrier that suppresses direct tunneling.
• Standby Power: In battery-powered devices, gate leakage from direct tunneling would drain the battery even when the chip is in standby — high-k dielectrics that suppress direct tunneling are essential for mobile and IoT applications.
• EOT Scaling: Even with high-k dielectrics, continuous EOT reduction eventually reintroduces direct tunneling through the interfacial SiO2 layer, creating an ongoing engineering challenge for each successive technology node.
• Test Structure Monitor: Direct tunneling current measured on gate capacitor test structures provides a sensitive monitor of gate dielectric thickness uniformity and quality across the wafer.

How Direct Tunneling Is Managed

• High-K Selection: Dielectrics with higher permittivity (HfO2 k~22, La2O3 k~27) can provide lower EOT than SiO2 while being physically thicker, suppressing direct tunneling at the same capacitance.
• Interface Layer Control: The thin SiO2 or SiON interfacial layer thickness is carefully minimized without compromising channel mobility or interface state density, as it is the primary direct tunneling path.
• Thickness Metrology: Ellipsometry, X-ray reflectivity, and TEM cross-section are used to monitor gate dielectric thickness to sub-angstrom precision, ensuring tunneling leakage remains within specification.

Direct Tunneling is the quantum physical wall that ended the SiO2 era — its unforgiving exponential dependence on oxide thickness forced one of the most technically demanding material transitions in semiconductor history and continues to constrain gate dielectric engineering at every advanced node.