Dummy Gate
A dummy gate is a temporary, sacrificial gate structure built during transistor fabrication purely to hold the channel's place through the high-temperature steps that would otherwise damage a real high-k metal gate — and then removed and replaced with the actual gate stack only once all that harsh processing is finished. It exists for one reason: the real high-k metal gate stack can't survive the thermal stress of source/drain implant annealing, so the gate-last process builds a disposable stand-in first, and swaps in the real gate only at the very end.
The dummy gate exists because the high-k metal gate stack is fundamentally incompatible with the high-temperature steps that come right after the gate is formed in a traditional process order. Building source and drain regions requires implanting dopants and then annealing the wafer at high temperature to activate them and repair implant damage — a step that happens with the gate already in place, since the gate itself helps define exactly where the source and drain regions form. High-k dielectrics and metal gate electrodes degrade badly under that thermal stress; the high-k material's properties shift, and the metal can react with surrounding materials in ways that ruin the gate's electrical behavior. A conventional polysilicon-on-silicon-dioxide gate tolerates this heat just fine, which is exactly why the industry reaches for a disposable polysilicon stand-in rather than trying to make high-k metal gates survive processing they were never designed to withstand.
The gate-last process, built around this dummy gate, runs almost the entire transistor fabrication sequence as if the dummy gate were the real one. The dummy gate — typically a thin dummy oxide topped with polysilicon or amorphous silicon — gets patterned at exactly the dimensions the final transistor needs, because it defines channel length and sets the spacer offset, the source, and the drain geometry during every subsequent step. Spacer formation, source/drain implantation, implant annealing, and silicidation all happen normally around this placeholder, exactly as they would around a genuine gate, because none of those process modules need to know or care that the gate standing in for the real one is only temporary.
Removing the dummy gate is one of the most unforgiving etch steps in the entire gate-last flow, because any damage to the channel underneath is unrecoverable. After chemical-mechanical polishing exposes the top of the dummy gate, a selective wet etch — typically an ammonium hydroxide etch for the polysilicon body, followed by hydrofluoric acid for the thin dummy oxide underneath — removes the entire structure while leaving the surrounding spacers completely intact. This etch has to stop precisely at the channel surface: too little removal leaves dummy material behind, contaminating the gate cavity; too much removal damages the channel itself, directly degrading the finished transistor's performance in a way that can't be fixed afterward.
What's left behind after the dummy gate is removed is an empty trench, lined by the spacers that were built around the original dummy structure, ready to receive the real gate stack. The high-k dielectric is deposited first, directly onto the freshly-exposed channel surface, followed by the metal gate electrode material, filling the cavity the dummy gate's removal created. Because this deposition happens only now — after every high-temperature step in the entire process is finished — the high-k metal gate stack never has to survive thermal stress at all, solving the incompatibility problem the dummy gate existed to work around in the first place.
The dummy gate's physical dimensions during the earlier process steps directly determine the final transistor's geometry, which is why getting its profile right matters as much as removing it cleanly. Dummy gate height and sidewall profile set the shape of the cavity the real gate stack eventually fills, so any variation in the dummy gate's dimensions during patterning propagates directly into variation in the finished transistor's gate geometry. This is a major reason gate-last processing, despite adding real complexity compared to a simpler gate-first approach, became the industry standard starting around the 45-32 nanometer generation: the benefit of letting the high-k metal gate stack go through the process completely undamaged outweighed the added cost and complexity of building, then discarding, an entire sacrificial gate structure first.