Embedded Multi-Die Interconnect Bridge
Interposers are the substrates that carry 2.5D integration: a die-to-die wiring layer dense enough to route thousands of connections between chiplets that sit side by side. The choice of interposer material and topology sets the achievable wiring pitch, the reachable die size, the warpage behaviour and most of the package cost.
Silicon interposers and the CoWoS family
A silicon interposer is a thinned wafer carrying damascene copper redistribution layers and through-silicon vias. Because it is patterned with wafer lithography, its wiring pitch is measured in single-digit micrometres, one to two orders finer than an organic substrate. TSMC's CoWoS family is the reference implementation and splits three ways:
| Variant | Bridge medium | Wiring pitch | Reticle-limited? | Typical use |
|---|---|---|---|---|
| CoWoS-S | full silicon interposer | ~0.4–1 µm RDL | yes — stitching needed beyond ~1× reticle | GPU + HBM, highest density |
| CoWoS-R | organic RDL interposer | ~2–5 µm | no | cost-sensitive, larger area, fewer HBM |
| CoWoS-L | local silicon bridges in organic | ~0.4–1 µm locally | no | large multi-die, mixed density |
CoWoS-L is the structural compromise that has become dominant for large accelerators. Full-silicon interposers run into the reticle limit: a modern accelerator plus eight HBM stacks exceeds the area a single exposure can pattern, forcing reticle stitching with its yield and alignment costs. CoWoS-L instead embeds small silicon bridges only where dense wiring is actually needed — between the compute die and each memory stack — and uses cheap organic RDL for everything else. Intel's EMIB is the same idea implemented by embedding the bridge die directly in the organic substrate.
The economics of area
Silicon interposer cost scales with area, and yield falls with it. For a defect density $D_0$ and area $A$, the Murphy yield model gives
Because the interposer is mostly wiring with few active devices its $D_0$ is low, but a $3\times$ reticle interposer is still a large, expensive piece of patterned silicon whose loss forfeits every known-good die mounted on it. This is why bridge approaches win as packages grow: they confine the expensive fine-pitch medium to a few square millimetres instead of a few thousand.
Warpage and CTE mismatch
The materials stacked in a 2.5D package expand at very different rates: silicon near 2.6 ppm/K, copper near 17, mould compound and organic substrate in the 15 to 18 range. Every excursion through reflow and every thermal cycle in the field therefore strains the assembly. A bonded pair behaves as a bimetallic strip, and the Timoshenko treatment gives a curvature
with $m = h_1/h_2$ the thickness ratio and $n = E_1/E_2$ the modulus ratio. The engineering consequence is that out-of-plane deflection scales roughly with the square of package length, so warpage is what actually caps package size — not lithography, not wiring. It manifests as non-wet joints at the die corners during reflow, cracked low-k dielectric under the bumps, and interposer fracture.
Mitigation is structural rather than clever: stiffener rings, balanced symmetric stack-ups, mould compounds tuned to sit between silicon and substrate, thicker interposers where flatness matters more than thermal resistance, and reflow profiles shaped to limit the peak $\Delta T$ the assembly must survive.
TSV density and keep-out
Through-silicon vias in the interposer carry power and signals from substrate to die. Their achievable density is limited less by lithography than by mechanics: copper in a silicon via expands far more than its surround, projecting a stress field into the silicon that shifts transistor mobility nearby. Designers therefore enforce a keep-out zone around each via, and that zone — not the via itself — sets the usable pitch. Because interposers carry few or no transistors, they tolerate much denser TSV arrays than an active die can, which is one more reason the function sits on a separate piece of silicon.