Feol
FEOL (Front End of Line) encompasses all semiconductor fabrication steps that create the active transistor devices on the silicon wafer — including well formation, isolation structures, gate stack engineering, source/drain implantation, and silicidation, building the fundamental switches that power every chip before metal interconnects are added.
What Is FEOL?
- Definition: The first major phase of semiconductor manufacturing, covering all process steps from bare silicon wafer to completed transistor structures — everything done before metallization (BEOL) begins.
- Scope: Well implants, STI (Shallow Trench Isolation), gate oxide growth, gate electrode formation, spacers, source/drain engineering, strain engineering, and contact silicidation.
- Duration: FEOL processing takes 4-8 weeks of the total 2-3 month fabrication cycle.
Why FEOL Matters
- Transistor Performance: FEOL defines transistor speed (drive current), power consumption (leakage), and density — the three most critical chip metrics.
- Node Definition: When we say "5nm node" or "3nm node," the defining feature is the FEOL transistor architecture (FinFET, GAA nanosheet).
- Yield Sensitivity: FEOL defects are the most costly — a contamination event during gate formation can scrap an entire wafer lot worth millions.
- Process Complexity: Leading-edge FEOL involves hundreds of process steps with sub-angstrom precision requirements.
Key FEOL Process Steps
- STI (Shallow Trench Isolation): Etches trenches between transistors and fills with SiO₂ to electrically isolate adjacent devices.
- Well Formation: Deep ion implantation creates N-wells and P-wells — large doped regions that define transistor type (NMOS in P-well, PMOS in N-well).
- Gate Stack: The most critical FEOL module — grows gate dielectric (HfO₂ high-k at advanced nodes) and deposits gate electrode (metal gate).
- Source/Drain Engineering: Ion implantation creates heavily doped regions adjacent to the gate — defines where current flows.
- Spacers: Si₃N₄ spacers formed on gate sidewalls define the gap between gate and source/drain implants.
- Strain Engineering: SiGe or SiC stressor regions increase carrier mobility for higher transistor speed — critical for performance.
- Silicidation: Metal-silicon compound (NiSi, TiSi₂) formed on source/drain and gate surfaces to reduce contact resistance.
FEOL Transistor Architectures
| Architecture | Nodes | Key Feature | Era |
|---|---|---|---|
| Planar MOSFET | >22nm | Flat channel | Pre-2012 |
| FinFET | 22-5nm | Vertical fin channel | 2012-2022 |
| GAA Nanosheet | 3nm and below | Stacked horizontal channels | 2022+ |
| CFET | Future (1nm?) | Stacked NMOS over PMOS | Research |
Critical FEOL Equipment
- Lithography: ASML (EUV, DUV) — defines pattern resolution.
- Etch: Lam Research, Tokyo Electron — creates transistor features.
- Deposition: Applied Materials, ASM International — gate stacks, spacers, strain layers.
- Ion Implant: Applied Materials (Varian), Axcelis — doping.
- Metrology: KLA, Hitachi, ASML (YieldStar) — critical dimension and overlay measurement.
FEOL is where transistors are born — the foundation of every processing chip, memory cell, and sensor, requiring the most advanced equipment and the tightest process control in all of manufacturing.