Floorplan Design Chip

Floorplan Design is the first and most consequential step in physical implementation — defining the chip boundary, placing hard macros (SRAM, analog IP, I/O pads), establishing power domain regions, creating the initial power grid, and setting up the routing topology — where decisions made in minutes at the floorplan stage determine timing closure outcomes that take weeks to change later.

Why Floorplanning Matters Most

A bad floorplan cannot be rescued by good placement and routing. Macro placement that blocks critical signal paths, power domains that fragment the routing fabric, or I/O placement that creates long cross-chip buses will persistently cause timing violations, congestion, and IR-drop hotspots throughout all downstream physical design stages.

Floorplan Elements

• Die/Block Size: Estimated from the gate count, macro area, and target utilization (typically 70-85% for standard cells). Oversizing wastes area and increases wire delay; undersizing causes routing congestion.
• Macro Placement: SRAMs, register files, PLLs, DACs/ADCs, and other hard macros are placed based on:
• Data flow affinity: Macros that exchange heavy traffic are placed adjacent to each other.
• Pin accessibility: Macro pins face toward the logic they connect to.
• Channel planning: Leave routing channels between macros for signal nets to pass through.
• I/O Pad Ring: I/O pads are placed around the die periphery following the package pin assignment. The pad ring order must match the package substrate routing to minimize bond wire length or bump-to-pad routing.
• Power Domain Partitioning: Each UPF power domain is assigned a contiguous region. Power switch cell arrays are placed along the domain boundary. Isolation and level shifter cells are placed at domain crossings.
• Blockage and Halo Regions: Placement blockages prevent standard cells from being placed in specific areas (e.g., under analog macros sensitive to digital noise). Halos around macros provide routing clearance.

Power Grid Planning

• Power Stripe Pitch: Global VDD/VSS stripes on upper metals are spaced to meet the IR-drop budget (<5% voltage drop at worst-case current). Denser stripes reduce IR drop but consume routing tracks.
• Power Domain Rings: Each voltage domain gets its own power ring (metal frame) connecting to the global grid through power switches.
• Decoupling Capacitance: Decap cells are placed in empty spaces to reduce supply noise (Ldi/dt) during high-activity switching events.

Floorplan Validation

Before proceeding to placement: estimate wirelength (half-perimeter bounding box), check routing congestion (global route estimation), verify macro pin accessibility, and run early-stage IR-drop analysis. Iterating on the floorplan is 100x faster than debugging timing failures after routing.

Floorplan Design is the architectural blueprint of the physical chip — a decision made in the first hour of physical design that echoes through every subsequent step, determining whether timing closure takes days or months.