Forksheet Logic Introduce the Dielectric Wall as Forksheets Defining Structural Trick

# Forksheet Transistors: Step 2 — Introduce the Dielectric Wall as Forksheet's Defining Structural Trick

## 1. The Single Structural Addition

Forksheet's entire identity as an architecture rests on one addition to the nanosheet GAA stack: a thin dielectric wall inserted directly between the NMOS and PMOS nanosheet stacks, running the full height of the gate structure at the exact boundary where the two device types meet. Everything else about the stack — sheet count, sheet release, inner spacers, source/drain epitaxy — is unchanged from the nanosheet baseline this series inherits from `gaa_nanosheet_2020s`.

## 2. Why a Wall Beats Open Space

Open space does its isolation job by distance alone: far enough apart, and the two gate structures simply cannot interact. A solid dielectric wall does the same isolation job at a fraction of the distance, because it physically blocks work-function-metal migration and provides a hard dielectric barrier against gate-to-gate leakage that empty space can only approximate by being wide. The wall trades width for material; it does not eliminate isolation, it makes isolation denser.

## 3. Why It Looks Like a Fork

In cross-section, the dielectric wall sits between the two nanosheet stacks like the single tine separating two outer tines of a fork, with the gate's conductive fill occupying the two outer channels on either side of that dividing tine. That visual is where the name comes from, and it is a literal description of the geometry, not a metaphor layered on afterward — the wall is the fork's middle structure, physically separating what would otherwise be one continuous gate cavity into two isolated halves.

## 4. One Gate Structure, Two Metals

Critically, forksheet still builds both devices within what is nominally a single gate structure footprint — the wall subdivides that footprint rather than creating two independent gate structures the way unmodified nanosheet GAA does with its open gap. That subdivision is what lets the two device types sit closer together than separate, fully independent gate structures ever could, while still keeping their work-function metals from touching.

The Dielectric Wall, in Cross-Section forksheet's one structural addition to the nanosheet baseline PMOS nanosheet stack dielectric wall NMOS nanosheet stack single gate structure, two separately tuned work-function metals, one thin dielectric wall between them the wall subdivides one gate footprint into two isolated halves visually, the wall is the middle tine of a fork — the source of the architecture's name
Forksheet Transistors: Step 2 — Introduce the Dielectric Wall as Forksheet's Defining Structural Trick Dielectric isolation wall, reduced N-to-P spacing, and standard-cell scaling THE SINGLE STRUCTURAL ADDI... Silicon Substrate n-Sheets Wall p-Sheets Dielectric Wall Spine <15nm Forksheet's entire identity as an architecture rests on one addition to the nanosheet GAA stack: a thin dielectric wall inserted directly between the NMOS WHY A WALL BEATS OPEN SPACE Silicon Substrate n-Sheets Wall p-Sheets Dielectric Wall Spine <15nm Open space does its isolation job by distance alone: far enough apart, and the two gate structures simply cannot interact. WHY IT LOOKS LIKE A FORK Silicon Substrate n-Sheets Wall p-Sheets Dielectric Wall Spine <15nm In cross-section, the dielectric wall sits between the two nanosheet stacks like the single tine separating two outer tines of a fork, with the gate's Key Semiconductor Engineering Takeaway A tall, narrow dielectric spine between NMOS and PMOS allows three-sided gate wrapping on each side of the fork. Provides a self-aligned physical stop for work-function metal patterning and prevents lateral dopant bridging.

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