Full Wafer Test

Full wafer test is the comprehensive probe operation where all dies on a wafer are electrically tested according to the full sort program before dicing - it maximizes defect screening coverage at the expense of test time.

What Is Full Wafer Test?

• Definition: Execute complete test plan over all reachable die sites using probe cards and automated test equipment.
• Coverage Goal: Validate functionality and key parametrics for each die.
• Parallelism: Multi-site probe cards test several dies simultaneously.
• Output: Complete wafer map with pass/fail and bin assignments.

Why Full Wafer Test Matters

• Maximum Screening: Detects broad failure modes before packaging.
• Yield Accounting: Provides accurate die-level quality and yield metrics.
• Risk Reduction: Minimizes chance of packaging defective dies.
• Process Diagnostics: Spatial failure patterns expose fab process excursions.
• Traceability: Full data supports root-cause and reliability investigations.

Execution Elements

Prober and Probe Card Setup:
- Align needles to wafer pads and verify contact integrity.
- Control site count and touchdown strategy.

Test Program Sequencing:
- Run structural, parametric, and functional vectors.
- Capture measurements for binning rules.

Wafer Map Generation:
- Record outcomes per die location.
- Feed MES and downstream packaging selection.

How It Works

Step 1:
- Step across wafer die sites, execute full electrical test suite, and collect data.

Step 2:
- Classify each die by binning criteria and output complete wafer sort map.

Full wafer test is the highest-coverage pre-package screening approach that prioritizes product quality and defect visibility - when cost allows, it provides the strongest early filter against downstream failures.