Fuse Antifuse Otp
Fuse, Antifuse, and OTP (One-Time Programmable) Memory are the non-volatile storage elements integrated into CMOS chips that can be permanently programmed once after manufacturing — used for chip ID, security keys, memory repair addresses, analog trimming values, and configuration data, where the permanent and irreversible nature of programming provides both tamper resistance and the ability to customize each chip individually during test and packaging.
Types of OTP Elements
| Type | Mechanism | Program Method | Read Method |
|---|---|---|---|
| Poly fuse | Blow polysilicon link (melt) | High current pulse | Resistance measurement |
| Metal fuse | Blow metal link (electromigration) | Current pulse | Resistance measurement |
| eFuse (electrical) | Electromigrate silicided poly | Moderate current | Resistance change |
| Antifuse | Break thin oxide | High voltage pulse | Resistance (low after break) |
| OTP bitcell | Modified MOSFET (gate oxide break) | Voltage stress | Transistor Vt shift |
eFuse (Most Common in Modern CMOS)
- Programming: Apply ~1.2V × 10mA for 10-100 µs → current melts silicide → poly link opens.
- Read: Sense resistance → low = '0' (intact), high = '1' (blown).
- Size: ~1-2 µm² per bit in advanced CMOS.
- Reliability: Resistance ratio >100:1 → robust read margin.
Antifuse
- Programming: Apply 5-8V across thin oxide → dielectric breakdown → conductive path forms.
- Opposite of fuse: Starts open, becomes closed after programming.
- Advantage: Very small area (~0.1 µm² per bit), high density.
- Used in: FPGA routing (antifuse-based FPGAs), security keys.
Applications
| Application | Bits Needed | Why OTP |
|---|---|---|
| Memory repair | 100-1000 | Store redundant row/column addresses |
| Chip ID / serial number | 64-128 | Unique identification |
| Security keys / root of trust | 128-256 | Tamper-resistant key storage |
| Analog trim (bandgap, PLL) | 10-50 | Compensate process variation |
| Configuration (speed bin) | 8-32 | Sorted after test |
| Feature enable/disable (SKU) | 8-32 | Product differentiation |
Memory Repair Flow
1. Test: MBIST identifies failing SRAM rows/columns.
2. Analyze: Repair algorithm selects optimal redundant row/column assignments.
3. Program: Blow eFuses encoding repair addresses.
4. Verify: Re-read fuses → confirm correct programming.
5. Retest: Run MBIST again → failing cells now redirected to redundant cells → chip passes.
Security Considerations
- eFuse: Physically visible under SEM → can be reverse-engineered.
- Antifuse: Oxide breakdown not easily visible → better for security.
- Both: One-time only → cannot be overwritten → tamper evidence.
- Key storage: Program AES/RSA keys → chip boots only with correct key → secure boot.
Comparison with Flash OTP
| Feature | eFuse | Antifuse | Embedded Flash OTP |
|---|---|---|---|
| Area per bit | 1-2 µm² | 0.1-0.5 µm² | 0.5-1 µm² |
| Program voltage | ~1.2V (low) | 5-8V (high) | 10-15V |
| Extra masks | 0 | 0-1 | 3-5 |
| Process compatibility | Standard CMOS | Standard CMOS | Needs flash module |
| Density | Low-medium | High | High |
Fuse and antifuse OTP elements are the permanent personalization technology that transforms identical silicon dice into individually configured products — from storing repair addresses that rescue otherwise failing memories to holding the cryptographic keys that anchor hardware security, OTP elements provide the non-volatile, tamper-resistant, zero-additional-mask-cost storage that every modern chip requires for post-fabrication customization.