Gate Level Simulation
Gate-Level Simulation (GLS) is the functional and timing verification technique that simulates the chip design at the synthesized netlist level with actual gate delays annotated from the Standard Delay Format (SDF) file — bridging the gap between fast RTL simulation (which ignores physical delays) and static timing analysis (which doesn't verify functionality), catching timing-dependent functional bugs like race conditions, glitches, and clock domain crossing errors that neither RTL simulation nor STA alone can detect.
Why Gate-Level Simulation
- RTL simulation: Verifies function → zero delay → cannot catch timing bugs.
- STA: Verifies timing → but assumes correct function → cannot catch functional bugs.
- GLS: Verifies function WITH timing → catches bugs that require both together.
- Examples: Glitch causes spurious latch capture, racing paths cause wrong data selection, async reset releases at wrong time.
GLS Flow
[Gate Netlist (.v)] + [SDF File (.sdf)] + [Testbench]
from Synthesis/PnR from Timing Analysis same as RTL
↓ ↓ ↓
[Gate-Level Simulator (VCS, Xcelium, QuestaSim)]
↓
[Compare outputs vs. RTL golden reference]SDF Annotation
// SDF file snippet
(CELL
(CELLTYPE "AND2X1")
(INSTANCE u_core/u_alu/g123)
(DELAY
(ABSOLUTE
(IOPATH A Y (0.025:0.030:0.038) (0.020:0.025:0.032))
(IOPATH B Y (0.028:0.033:0.042) (0.022:0.028:0.036))
)
)
)- SDF contains: Cell delays, interconnect delays, setup/hold timing checks.
- Min:Typ:Max values for each delay → simulate at each corner.
- Back-annotated from actual layout parasitics → physically accurate.
Types of GLS
| Type | Delays | Catches | Runtime |
|---|---|---|---|
| Zero-delay GLS | No delays | Structural bugs (missing connections) | 2-5× RTL |
| Unit-delay GLS | All delays = 1 unit | Basic race conditions | 3-7× RTL |
| Full-timing GLS (SDF) | Actual gate + wire delays | All timing-dependent bugs | 10-100× RTL |
| Back-annotated GLS | Post-PnR parasitics | Most accurate, signoff quality | 50-200× RTL |
Bugs Found by GLS (Not by RTL Sim or STA)
| Bug Type | Why RTL Misses | Why STA Misses |
|---|---|---|
| Glitch on clock gate enable | Zero-delay enable is clean | STA checks setup/hold, not glitch |
| Race between reset and clock | Reset and clock are concurrent in RTL | STA doesn't simulate async reset |
| CDC data corruption | RTL model assumes instant synchronization | STA flags but doesn't simulate |
| Timing-dependent MUX select | MUX select arrives same cycle → RTL picks one arbitrarily | STA verifies paths independently |
| Init sequence timing | Power-on sequence has no delay in RTL | STA doesn't cover power-on |
Practical Challenges
| Challenge | Impact | Mitigation |
|---|---|---|
| Runtime | 50-200× slower than RTL | Reduce test vector set, use targeted tests |
| X-propagation | Uninitialized signals create X → masks bugs or causes false failures | Use X-prop simulation mode |
| Memory models | Large memories slow simulation | Use behavioral memory models |
| Analog interfaces | GLS cannot model analog behavior | Black-box analog blocks |
| Debug | Gate-level waveforms harder to read | Cross-reference to RTL hierarchy |
Gate-level simulation is the verification safety net that catches the timing-functional interaction bugs that slip through all other verification methods — while STA ensures timing correctness under assumed functionality and RTL simulation verifies functionality under ideal timing, GLS is the only method that verifies both together, making it an indispensable step for taping out reliable silicon despite its significant runtime cost.