Gate Spacer Engineering
Gate Spacer Engineering is the precise design and fabrication of dielectric sidewall structures adjacent to the gate electrode that control transistor parasitic capacitance, junction placement, and reliability — one of the most critically tuned elements in advanced CMOS, where the spacer's dielectric constant, thickness, and composition directly set the speed-power tradeoff of every logic gate on the chip. At sub-10nm nodes, gate spacer optimization delivers 10–20% performance improvement simply by reducing the gate-to-drain capacitance (Cgd) that limits switching speed.
Gate Spacer Functions
- Mechanical: Protects gate sidewalls during source-drain implant or epitaxial growth.
- Electrical (parasitic capacitance): Spacer dielectric between gate and source/drain sets Cgd — lower k → lower capacitance → faster switching.
- Junction offset: Spacer width controls distance of source/drain from gate edge → sets overlap capacitance and short-channel effects.
- Silicide offset: Keeps nickel or cobalt silicide away from gate edge → prevents gate-to-S/D shorts.
- Reliability isolation: Separates high-field gate edge from contact metals.
Spacer Dielectric Options
| Material | Dielectric Constant (k) | Integration Advantage | Integration Challenge |
|---|---|---|---|
| Si₃N₄ | 7–8 | High etch selectivity | High capacitance |
| SiO₂ | 3.9 | Low capacitance | Poor etch selectivity |
| SiOCN | 4–5.5 | Tunable k, good selectivity | Film quality control |
| SiCO | 3–4.5 | Lower k | Weaker mechanically |
| Air gap | ~1 | Lowest possible capacitance | Process complexity |
Spacer Sequence in FinFET Process
1. Gate patterning (poly or metal gate defined)
2. Offset spacer deposition (thin SiO₂ or SiN, 2–5 nm)
3. Extension implant or epi growth (LDD / S/D extension)
4. Main spacer deposition (SiN or SiOCN, 5–15 nm)
5. Spacer etch-back (anisotropic RIE → leaves sidewall only)
6. Source-drain recess + SiGe or Si:P epitaxy
7. (Optional) Spacer trim to control final widthLow-k Spacer at Advanced Nodes
- 7nm: Transition from SiN (k=7) to SiOCN (k=4.5) → reduced Cgd → +5–8% frequency at iso-power.
- 5nm: Dual-spacer approach: thin SiO₂ offset + SiOCN main spacer.
- 3nm/2nm (Nanosheet): Inner spacer between gate and source-drain is even more critical — low-k SiOCN or SiCO inner spacer reduces parasitic capacitance at the gate-drain interface of each nanosheet layer.
Inner Spacer (GAA-Specific)
- In gate-all-around (nanosheet) transistors, after SiGe release, cavities remain between nanosheet layers.
- Inner spacer deposited in these cavities by ALD → isotropic etch-back to define spacer geometry.
- Inner spacer k value directly controls the dominant parasitic capacitance in nanosheet FETs.
- SiOCN (k~4.5) or SiCO (k~3.5) are the materials of choice for inner spacers at 2nm.
Air Gap Spacer
- Ultimate low-k: Enclose an air void (k=1) within the spacer region.
- Process: Deposit sacrificial spacer → gate-last flow → selective removal of sacrificial material → seal with thin cap.
- Used experimentally at IMEC, IBM; Intel demonstrated air-gap spacers in research.
- Challenge: Structural integrity, filling during subsequent depositions.
Gate spacer engineering is a silent but decisive factor in transistor performance — the choice of spacer material and geometry at each node accounts for a significant fraction of the performance gain marketed as the benefit of a new technology node, making it one of the highest-leverage integration decisions in advanced CMOS development.