Groq

Custom AI Accelerator Chips

AI Chip Landscape
| Company | Chip | Focus |
|---------|------|-------|
| NVIDIA | H100, B200 | General AI |
| Groq | LPU | Low-latency inference |
| Cerebras | WSE-3 | Largest chip, training |
| Google | TPU v5 | Google Cloud AI |
| AWS | Trainium/Inferentia | AWS workloads |
| AMD | MI300X | NVIDIA alternative |

Groq LPU — Deterministic Inference at SRAM Speed no HBM, no caches, no speculation — pure SRAM + compiler-scheduled dataflow = predictable latency TSP (Tensor Streaming Processor) 230 MB SRAM (on-die) no HBM, no DRAM — entire model weights in SRAM 80 TB/s internal bandwidth (vs 3.35 TB/s HBM on H100) VXM (Vector Unit) SIMD + scatter/gather MXM (Matrix Unit) 320×320 systolic Streaming interconnect (compiler-scheduled, no arbitration) Deterministic execution: every cycle mapped at compile time No cache misses. No stalls. No variability. compiler does the scheduling (like VLIW), not hardware Why Groq is Fast (Inference Only) SRAM bandwidth: 80 TB/s (vs 3.35 TB/s HBM) → decode phase is memory-BW limited → 20x more BW = faster Deterministic latency: every token same speed → no P99 tail latency spikes (great for real-time) Result: ~500 tokens/s per user (Llama-3 70B) (vs ~80 tokens/s on H100 vLLM for same model) Trade-offs ✗ Small memory (230 MB) — model must be distributed Llama-3 70B needs ~576 chips (memory-limited) ✗ No training — inference only (fixed dataflow) ✗ Limited model architectures (MoE harder) Sweet spot: dense decoder-only LLMs at inference AI Accelerator Landscape (Inference) NVIDIA H100 80 GB HBM3 general purpose train + infer Groq LPU 230 MB SRAM fastest tokens/s infer only Google TPU 32-95 GB HBM systolic, JAX only train + infer Cerebras WSE 40 GB SRAM (wafer) largest die ever train + infer Groq: API available (GroqCloud), competitive pricing for inference-heavy workloads Groq's bet: for inference, memory bandwidth matters more than compute — so replace HBM with on-die SRAM Groq sacrifices generality for speed: a chip that does one thing (LLM decode) faster than anything else.

Groq LPU (Language Processing Unit)

Architecture
- Deterministic silicon: No caching, no variable latency
- SRAM-based: Large on-chip memory
- Tensor streaming: Optimized for sequential ops

Performance Claims
| Metric | Claim |
|--------|-------|
| Latency | <100ms first token |
| Throughput | 500+ tokens/sec |
| Power efficiency | High tokens/watt |

Groq API

from groq import Groq

client = Groq()

response = client.chat.completions.create(
    model="llama-3.2-90b-vision-preview",
    messages=[{"role": "user", "content": "Hello!"}]
)
print(response.choices[0].message.content)

Cerebras WSE (Wafer Scale Engine)

Unique Architecture
- Entire wafer as one chip (46,225 mm^2)
- 900,000 cores
- 40GB on-wafer memory
- Designed for massive models

Use Cases
- Training large models (no model parallelism needed)
- Drug discovery
- Climate modeling

Comparison
| Chip | Strength | Weakness |
|------|----------|----------|
| NVIDIA H100 | Ecosystem, flexibility | Cost, power |
| Groq LPU | Latency | Model size limits |
| Cerebras WSE | Large models | Specialization |
| TPU v5 | Google integration | Vendor lock-in |
| Trainium | AWS cost savings | AWS only |

When to Consider
| Use Case | Recommended |
|----------|-------------|
| General purpose | NVIDIA |
| Ultra-low latency | Groq |
| Massive training | Cerebras |
| Cloud provider | TPU/Trainium |
| Cost optimization | AMD/Trainium |

Best Practices
- Start with NVIDIA for flexibility
- Evaluate specialized hardware for specific needs
- Consider total cost (chips + development)
- Watch for SDK maturity
- Plan for vendor transitions

Take groq further

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