Base Logic Die

The base logic die is the bottom die of an HBM stack: the layer that aggregates every TSV column from the DRAM dies above it, runs the physical interface to the host, and handles test, repair and power management for the whole stack. With HBM4 it stops being a DRAM-process part and becomes a logic-process part, and that change reshapes both the architecture and the supply chain.

What it does

The DRAM core dies above it are optimised for bit density and nothing else. Everything that is not storing a bit lives on the base die:

  • the PHY driving 1024 or 2048 bits to the host across the interposer
  • TSV aggregation and per-channel routing from sixteen or more independent channels
  • built-in self-test, redundancy mapping and post-package repair
  • power management, on-die regulation, and thermal sensing
  • the direct-access test path that lets a stack be characterised before assembly
HBM4 Base Logic Die — A Logic Part Under a Memory Stack two foundries, two process families, one stack DRAM core dies — memory foundry process TSV columns BASE LOGIC DIE PHY · TSV aggregation · BIST/repair · PMIC logic foundry — FinFET / nanosheet process interposer — 2048-bit bus to host every DRAM die above is purely bit storage — everything that isn't storing a bit has been pushed down into this one die, which is why it had to leave the DRAM process to fit

Why HBM4 moved it to a logic node

Through HBM3E the base die was fabricated on a DRAM-like process. DRAM processes are built around the capacitor and the retention budget; their transistors are comparatively slow and their metal stacks are thin. A 2048-bit PHY running at multi-gigabit rates is a large, fast, dense logic block, and building it on a DRAM process costs area and power that a logic process does not.

The energy argument is the decisive one. Interface energy is dominated by charging the channel capacitance each transition:

$$ E_{\text{bit}} = \alpha\, C_{\text{eff}} V_{DD}^{2} $$

A logic process offers both a lower $V_{DD}$ and denser, lower-capacitance wiring, and the quadratic in supply voltage means a modest voltage reduction is a large energy saving. Total interface power then scales as

$$ P_{\text{PHY}} = E_{\text{bit}} \times BW \times 8 $$

and at 2 TB/s that product is large enough that a fraction of a picojoule per bit decides whether the stack fits its thermal envelope. Thermal headroom is not abstract here: DRAM retention is exponential in temperature — the same Arrhenius relationship this project's DRAM series has already traced from the storage capacitor's own decay equation — so every watt dissipated in the base die shortens the refresh interval of the dies stacked directly above it.

That thermal coupling is the real architectural cost of moving power-hungry logic to the bottom of the stack. The base die sits furthest from the package's heat spreader, so any heat it generates has to conduct upward through every DRAM die and every TSV/hybrid-bond interface stacked above it before it reaches anywhere cooler — a long, high-resistance path that a low-power, PHY-only base die never had to worry about.

The Base Die Sits at the Bottom of Its Own Worst Thermal Path every watt it dissipates has to climb through every die and bond interface above it die position in the stack, base to top → temperature rise ΔT → base top die retention-safe threshold base die — hottest, logic power, worst path to the heat spreader top die — closest to the heat spreader ΔT = P × ΣR_thermal — summed series resistance across every TSV and bond interface between here and the top

Custom base dies

Once the base die is a logic die, it can be customised per customer, and HBM4 is the generation where that becomes commercial practice. A buyer specifying their own base die can move function into the memory stack: scheduling and prefetch tuned to their access pattern, ECC schemes matched to their reliability target, compression and decompression at the memory boundary, and eventually arithmetic performed where the data already sits rather than after a round trip to the accelerator.

That last possibility is the interesting one. The bandwidth wall in transformer inference exists because weights must be streamed to the compute units and used once. Any operation that can be performed inside the stack removes traffic from the interface entirely, and the base die is the only place in an HBM stack with enough logic performance to host it.

One Standardized Stack, Two Different Customers' Base Dies the DRAM dies and TSV pitch stay a catalogue part — the base die becomes the customization layer customer A's stack identical, standardized DRAM dies base die — custom A prefetch tuned to A's access pattern customer B's stack base die — custom B near-memory compute, B's own kernels the DRAM dies never change — only the base die is re-spun per customer scheduling, ECC policy, compression, and near-memory compute all live on the one die that was already being re-fabricated per customer anyway — adding logic there is close to free any operation finished inside the stack is bandwidth that never has to cross the interface at all this is the real commercial shift HBM4 enables — memory stops being a catalogue part and becomes a co-designed one, without having to re-qualify a single DRAM die

What it costs

The stack is now a heterogeneous assembly spanning two foundries and two process families, bonded together, with yield and schedule coupled across companies that previously interacted only through a specification. A logic-node base die is also expensive relative to the DRAM above it, and it must be known-good before stacking, which raises the value of pre-bond test and post-package repair. Combined with the move from micro-bump to direct bond interconnect, HBM4 turns memory procurement into a co-design problem rather than a catalogue purchase — which is much of why HBM supply, not wafer capacity, has been the binding constraint on accelerator deployment.

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