Ild Dielectric Deposition
Inter-Layer Dielectric (ILD) Deposition is the process of depositing insulating films between metal interconnect layers — providing electrical isolation, mechanical planarization base, and enabling the multilayer metal stack that routes signals across a chip.
ILD Role in BEOL
- Between every metal layer: Via dielectric + interconnect dielectric.
- Provides electrical isolation between wiring levels.
- Filled by CMP to planarize before next lithography.
- Modern chips: 10–20 metal layers = 20–40 ILD deposition steps.
ILD Material Evolution
| Node | Dielectric | k value | Reason |
|---|---|---|---|
| > 250nm | Thermal SiO2 | 3.9 | Gold standard |
| 180nm | TEOS-PECVD SiO2 | 4.0 | Denser, conformal |
| 130nm–90nm | F-doped SiO2 (FSG) | 3.5 | Lower RC |
| 65nm–28nm | CDO/SiCOH | 2.7–3.0 | RC improvement |
| 14nm–5nm | Porous SiCOH | 2.5–2.6 | Ultra-low-k |
| Sub-5nm | Air gaps | ~1.0–2.0 | Air is k=1 |
TEOS (Tetraethylorthosilicate) Deposition
- Si(OC2H5)4 precursor → SiO2 + ethanol by-products at 400°C with O3 or O2.
- Ozone-TEOS (SA-TEOS): Excellent gap fill due to surface-migration.
- PECVD-TEOS: Better film density, lower moisture absorption vs. SiH4-based.
Low-k ILD Deposition
- Spin-on dielectrics (early low-k): Applied like photoresist — low density, poor mechanical strength.
- PECVD SiCOH: Carbon-doped oxide, porosity introduced by porogen burnout.
- Porogen: Organic molecules in film, burned out by UV or anneal → pores → lower k.
ILD Challenges at Advanced Nodes
- Ultra-low-k films (porous): Mechanically weak, prone to cracking during CMP.
- Air gaps: Self-forming during Cu CMP (TSMC, Intel at 7nm+).
- Moisture uptake: Porous ILD absorbs water → k increases over time.
- Integration: Low-k films incompatible with O2 plasma — ashing damages k-value.
ILD deposition is the backbone of the BEOL interconnect stack — its dielectric constant directly determines RC delay and thus the speed and power of every chip at frequencies above a few GHz.