Interconnect RC Delay Scaling
Interconnect RC Delay and BEOL Scaling Challenges are the growing performance bottleneck in advanced CMOS technology where shrinking metal line widths cause wire resistance to increase super-linearly due to grain boundary and surface scattering effects — creating a situation where transistor switching improves with each node but interconnect delay worsens, with RC delay now dominating total circuit delay at sub-7nm nodes and driving fundamental changes in metal materials, via technology, and circuit architecture.
The Interconnect Scaling Crisis
- Moore's Law: Transistors get faster with scaling → gate delay decreases.
- Interconnects: Thinner, narrower wires → resistance increases as 1/A (cross-section).
- Capacitance: Closer wires → higher coupling capacitance between adjacent lines.
- RC delay = R × C → increases with scaling even as transistors improve.
- At sub-7nm: Interconnect delay > gate delay → wire is the bottleneck.
Resistance Scaling Problem
| Metal Width | Cu Bulk ρ | Actual ρ (thin wire) | Increase | Cause |
|---|---|---|---|---|
| 100nm | 1.7 µΩ·cm | 2.0 µΩ·cm | 1.2× | Small grain boundary effect |
| 40nm | 1.7 µΩ·cm | 3.0 µΩ·cm | 1.8× | Grain boundary + surface |
| 20nm | 1.7 µΩ·cm | 5.5 µΩ·cm | 3.2× | Severe scattering |
| 12nm | 1.7 µΩ·cm | 10+ µΩ·cm | 6× | Approaching limit |
Why Resistance Increases
- Grain boundary scattering: Electrons scatter at Cu grain boundaries → smaller grains in narrow wires → more boundaries per unit length → higher resistivity.
- Surface scattering: Electrons scatter at wire-barrier interface → thinner wire → more surface relative to volume → higher resistivity.
- Barrier overhead: TaN/Ta barrier is ~3nm → in 12nm-wide wire, barrier takes 50% of width → only 6nm of Cu conducts.
Solutions Being Deployed
| Solution | Mechanism | Impact |
|---|---|---|
| Cobalt (local wires) | No barrier needed → more metal volume | Lower R at M0/M1 |
| Ruthenium | Short mean free path → less scattering | Better R at narrow widths |
| Molybdenum | Very short MFP, no barrier needed | Promising at <10nm |
| Air gap dielectric | Replace low-k with air (k=1) | Lower C by 30-50% |
| Self-aligned via | Reduce via resistance | Eliminate landing pad |
| Subtractive etch | Etch metal instead of damascene | Better grain structure |
Metal Comparison at Narrow Widths
| Metal | Bulk ρ (µΩ·cm) | MFP (nm) | ρ at 10nm width | Barrier Needed |
|---|---|---|---|---|
| Cu | 1.7 | 39 | 10+ | Yes (3-5nm) |
| Co | 6.2 | 12 | 12-15 | Minimal (1nm) |
| Ru | 7.1 | 6.7 | 10-13 | No |
| Mo | 5.3 | 14 | 9-12 | No |
| W | 5.3 | 20 | 12-16 | Minimal |
- At 10nm width: Ru/Mo without barrier ≈ Cu with barrier → metals are comparable!
- Below 10nm: Barrier-free metals win because barrier consumes too much Cu cross-section.
Capacitance Mitigation
- Low-k dielectrics: SiOCH (k=2.5-3.0) replaced SiO₂ (k=3.9).
- Ultra-low-k: Porous SiOCH (k=2.0-2.5) → fragile, integration challenges.
- Air gap: k=1.0 between wires → best capacitance but complex process.
- Back-end routing: Long wires in upper thick-metal layers (lower R and C per unit length).
Interconnect RC delay is the dominant performance limiter in modern CMOS and the primary driver of one of the most consequential material transitions in semiconductor history — the shift from copper to alternative metals (Co, Ru, Mo) at the tightest pitches, combined with air-gap dielectrics and self-aligned patterning, represents a complete reinvention of back-end-of-line technology that is as significant as the gate-first-to-gate-last transition was for front-end processing.