Interposer Technology

Interposers are the substrates that carry 2.5D integration: a die-to-die wiring layer dense enough to route thousands of connections between chiplets that sit side by side. The choice of interposer material and topology sets the achievable wiring pitch, the reachable die size, the warpage behaviour and most of the package cost.

Silicon interposers and the CoWoS family

A silicon interposer is a thinned wafer carrying damascene copper redistribution layers and through-silicon vias. Because it is patterned with wafer lithography, its wiring pitch is measured in single-digit micrometres, one to two orders finer than an organic substrate. TSMC's CoWoS family is the reference implementation and splits three ways:

VariantBridge mediumWiring pitchReticle-limited?Typical use
CoWoS-Sfull silicon interposer~0.4–1 µm RDLyes — stitching needed beyond ~1× reticleGPU + HBM, highest density
CoWoS-Rorganic RDL interposer~2–5 µmnocost-sensitive, larger area, fewer HBM
CoWoS-Llocal silicon bridges in organic~0.4–1 µm locallynolarge multi-die, mixed density

CoWoS-L is a structural compromise for large accelerators. Full-silicon interposers run into the reticle limit: a modern accelerator plus eight HBM stacks exceeds the area a single exposure can pattern, forcing reticle stitching with its yield and alignment costs. CoWoS-L instead embeds small silicon bridges only where dense wiring is actually needed — between the compute die and each memory stack — and uses cheap organic RDL for everything else. Intel's EMIB is the same idea implemented by embedding the bridge die directly in the organic substrate.

Where the Wires Actually Run — Full Interposer vs. Local Bridges top view: only the die shorelines need thousands of fine wires; power and long-haul routing can stay coarse full silicon interposer compute reticle-size die HBMHBMHBMHBM fine-pitch silicon and wafer processing under the whole package excellent routing freedom · cost and defect exposure scale with area organic substrate + local silicon bridges compute fine pitch only at edges HBMHBMHBMHBM small bridges carry dense shoreline traffic; organic RDL carries the rest package grows beyond one reticle without scaling silicon area with it The bridge is a routing concentrator: silicon-class density exactly where two die edges exchange data. Its penalty is discontinuity—fine-to-coarse transitions, bridge placement, bump escape, power delivery, and local stress must all close.

The economics of area

Silicon interposer cost scales with area, and yield falls with it. For a defect density $D_0$ and area $A$, the Murphy yield model gives

$$ Y = \left(\frac{1 - e^{-A D_0}}{A D_0}\right)^{2} $$

Because the interposer is mostly wiring with few active devices its $D_0$ is low, but a $3\times$ reticle interposer is still a large, expensive piece of patterned silicon whose loss forfeits every known-good die mounted on it. This is why bridge approaches win as packages grow: they confine the expensive fine-pitch medium to a few square millimetres instead of a few thousand.

Interposer Area — Yield Falls Before Wiring Runs Out Murphy yield model: a passive interposer has low defect density, but very large area still compounds exposure 01×2×3×4×5× reticle area 0%25%50%75%100% patterned silicon area → interposer yield → low effective defect density moderate defect density process excursion / stitching penalty why one interposer loss is expensive known-good compute and HBM are attached later but interposer test, assembly, and package yield multiply large silicon also consumes scarce wafer-level capacity bridges confine fine-pitch defect exposure to shorelines the toll bridge fine routing + large-area lithography + TSV sold as qualified package yield, not raw silicon Curves illustrate Murphy-model sensitivity; exact yield depends on process-specific defect density and stitching quality.
Interposer Topologies: Full Silicon vs Embedded Bridge put the expensive fine-pitch medium only where the wires are dense CoWoS-S — full silicon HBM compute die silicon interposer — whole area organic substrate reticle-limited · cost ∝ area CoWoS-L / EMIB — local bridge HBM compute die Si bridge organic RDL organic substrate no reticle limit · dense only where needed Warpage: the CTE mismatch that limits package size κ ∝ Δα · ΔT Si 2.6 ppm/K · Cu 17 ppm/K · organic substrate 15–18 ppm/K curvature grows with L² — large packages warp, joints open at the corners

Warpage and CTE mismatch

The materials stacked in a 2.5D package expand at very different rates: silicon near 2.6 ppm/K, copper near 17, mould compound and organic substrate in the 15 to 18 range. Every excursion through reflow and every thermal cycle in the field therefore strains the assembly. A bonded pair behaves as a bimetallic strip, and the Timoshenko treatment gives a curvature

$$ \kappa = \frac{6\,(\alpha_2 - \alpha_1)\,\Delta T\,(1+m)^2}{h\left[3(1+m)^2 + (1+mn)\left(m^2 + \dfrac{1}{mn}\right)\right]} $$

with $m = h_1/h_2$ the thickness ratio and $n = E_1/E_2$ the modulus ratio. The engineering consequence is that out-of-plane deflection scales roughly with the square of package length, so warpage is what actually caps package size — not lithography, not wiring. It manifests as non-wet joints at the die corners during reflow, cracked low-k dielectric under the bumps, and interposer fracture.

Mitigation is structural rather than clever: stiffener rings, balanced symmetric stack-ups, mould compounds tuned to sit between silicon and substrate, thicker interposers where flatness matters more than thermal resistance, and reflow profiles shaped to limit the peak $\Delta T$ the assembly must survive.

TSV density and keep-out

Through-silicon vias in the interposer carry power and signals from substrate to die. Their achievable density is limited less by lithography than by mechanics: copper in a silicon via expands far more than its surround, projecting a stress field into the silicon that shifts transistor mobility nearby. Designers therefore enforce a keep-out zone around each via, and that zone — not the via itself — sets the usable pitch. Because interposers carry few or no transistors, they tolerate much denser TSV arrays than an active die can, which is one more reason the function sits on a separate piece of silicon.

Routing density is local; qualification is global

A local bridge saves silicon area because only die shorelines need the finest wiring. It does not make the package easy: bridge placement, two bump-pitch regimes, fine-to-coarse escape routing, power delivery, substrate warpage and signal return paths must be qualified together. Intel describes EMIB as using tight pitch at the bridge while allowing looser pitch across the rest of the die/core region, and reports the technology in high-volume manufacturing since 2017.

The economic moat is the verified package design kit and assembly window. Customers buy known routing rules, insertion loss, power integrity, mechanical reliability and assembly yield across a large multi-die structure—not merely a small piece of passive silicon.

References

  • Intel Foundry, “EMIB Technology Brief” (2025).
  • Intel Foundry, “Advanced Packaging Innovations” (accessed 2026).
  • Intel Foundry, “Building Intel’s Foundry Ecosystem for the AI Era” (2024).

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