Leakage Current

Leakage current is the current that flows through a transistor even when it's fully switched off, and it exists for several distinct physical reasons rather than one — subthreshold conduction, gate-oxide tunneling, and reverse-biased junction leakage all contribute, each through a completely different mechanism. None of these individually look large on a single transistor, but multiplied across the billions of transistors on a modern chip, leakage current has become one of the largest single contributors to total chip power, especially on anything that spends significant time idle.

Subthreshold leakage is the dominant leakage mechanism in most designs, and it's a direct, unavoidable consequence of how a transistor turns on in the first place. A transistor doesn't switch from fully off to fully on instantly as gate voltage crosses threshold voltage — conduction rises exponentially as gate voltage approaches threshold, meaning some current still flows even below it, just exponentially less. This relationship is brutally sensitive: lowering threshold voltage by roughly 100 millivolts typically increases subthreshold leakage by about tenfold. That exponential sensitivity is exactly why threshold voltage can't simply be lowered for faster switching without a severe leakage penalty, and it's the core tension underlying almost every leakage-versus-performance tradeoff in modern transistor design.

Gate leakage comes from quantum tunneling straight through the gate oxide, and it was once a genuine crisis before the industry fixed it with a materials change rather than a circuit trick. As gate oxide thickness shrank toward just a few atomic layers, electrons began tunneling directly through the oxide even though it should, classically, be a perfect insulator — current leaking straight through the gate terminal that was never part of the transistor's intended operation at all. The high-k metal gate transition, replacing silicon dioxide with physically thicker materials like hafnium oxide that deliver the same electrostatic control at a much lower tunneling risk, effectively eliminated gate leakage as a dominant concern once it was broadly adopted at the 45-nanometer node and beyond.

Junction leakage and gate-induced drain leakage (GIDL) are smaller contributors individually, but they matter because they respond to different knobs than subthreshold leakage does. Junction leakage is simple reverse-bias current flowing across the diode formed between heavily-doped source/drain regions and the surrounding substrate — it rises with temperature, which is why leakage power is always worse on a hot chip than a cold one. GIDL is a more exotic mechanism specific to the overlap region between gate and drain, where band-to-band tunneling can occur when drain voltage is high and gate voltage is low (exactly the "off" condition a digital circuit spends most of its time in) — making GIDL worse specifically under the high-supply-voltage conditions that performance-focused designs want to use.

At advanced process nodes, leakage stopped being a rounding error and became a first-order design constraint in its own right. At 7 nanometers and below, leakage power can account for 30 to 50 percent of a chip's total power budget — and on a modern advanced-node chip packed with billions of transistors, aggregate leakage alone can reach tens of watts even while the chip is sitting idle. This is the real reason chip power consumption stopped scaling down proportionally with Moore's Law-era transistor shrinkage: even as each individual transistor got smaller and leakier in relative terms, the sheer number of transistors on a chip grew fast enough that total leakage power kept climbing rather than falling.

Managing leakage now requires attacking it from multiple directions simultaneously, because no single fix addresses every leakage mechanism at once. Multi-threshold-voltage cell libraries let designers use higher-threshold, lower-leakage cells on non-critical timing paths while reserving faster, leakier cells only where speed genuinely matters. Power gating cuts supply voltage entirely to blocks that are temporarily idle, eliminating their leakage completely rather than just reducing it. Adaptive body biasing raises threshold voltage dynamically during idle periods and lowers it during active computation, trading leakage for speed in real time rather than fixing the choice at design time. And the architectural shift to FinFET and gate-all-around transistors directly reduces subthreshold leakage at its source, by giving the gate a tighter electrostatic grip on the channel than a planar transistor's geometry ever could.