Line Edge Roughness Measurement

Line edge roughness (LER) measurement quantifies how much a patterned feature's actual edge wanders randomly away from its intended straight or smooth path — measured by scanning a line's edge at many points along its length with CD-SEM and computing the statistical spread of those edge positions. LER doesn't shrink proportionally as features shrink the way most dimensions do, which means the exact same physical roughness becomes a dramatically larger fraction of a feature's total width at every new, smaller process node.

CD-SEM measurement, scanning a line's edge at many discrete points along its length, is the standard LER measurement approach because it directly captures the actual edge position variation that defines roughness in the first place. Rather than measuring a line's width at just one or two locations, CD-SEM samples the edge position repeatedly along the full length of a line, building up a statistical picture of exactly how much that edge genuinely wanders from point to point rather than running perfectly straight. This dense point-by-point sampling is what lets LER actually be computed as a meaningful statistical quantity rather than estimated from a handful of isolated measurements.

Reporting LER as three standard deviations (3σ) of the measured edge-position distribution, rather than as a simple average deviation, captures the real statistical spread that actually matters for predicting device impact. A simple average could understate how far edges genuinely wander if the distribution has a long tail, while 3σ specifically captures a wide statistical range encompassing the great majority of the actual variation observed. This convention exists because what matters for transistor-to-transistor variation isn't the typical edge deviation — it's how far edges can realistically wander in the worst realistic cases, which 3σ reporting captures far better than a simple mean deviation would.

Power spectral density (PSD) analysis decomposes the roughness signal into its different spatial frequency components, revealing whether a given line's roughness comes from fine-grained, high-frequency noise or from slower, longer-wavelength wandering — information a single 3σ number alone simply can't provide. Two lines with identical overall 3σ LER values can have completely different underlying roughness character: one might show mostly rapid, small-scale fluctuation, while the other shows the same total variation concentrated in slower, broader wandering. These two roughness characters can affect device performance differently, which is exactly why PSD analysis matters beyond the single aggregate LER number alone.

Correlation length describes the characteristic distance over which edge positions remain statistically related to each other, providing a complementary piece of information to PSD that captures roughness's spatial "memory" directly. A short correlation length means the edge position at one point tells you very little about the edge position a short distance away — rapid, largely independent fluctuation. A longer correlation length means edge positions nearby remain related over a greater distance — slower-varying, more correlated wander. This spatial-memory characteristic, alongside the PSD's frequency-domain view, gives a genuinely complete picture of how a line's roughness actually behaves, beyond what the single aggregate 3σ value alone can convey.

LER's failure to scale down proportionally with feature size is exactly why it has become a dominant source of transistor-to-transistor variability at advanced nodes, even though the absolute physical roughness itself hasn't necessarily gotten worse. A fixed amount of physical edge roughness — say, 2 nanometers — represents a modest 10 percent of a 20-nanometer line's width, but the exact same 2 nanometers of roughness becomes a dominating 40 percent of a 5-nanometer line's width. Because LER directly causes transistor-to-transistor threshold voltage variation (channel width variation translates into electrical performance variation), this relative worsening with each shrinking node is a primary reason device variability has become such a serious concern at the most advanced process nodes — not because roughness itself got worse in absolute terms, but because the features it sits on kept shrinking around it.