Line Width Roughness (Lwr)
Line width roughness is the statistical variation of the physical distance between opposing edges of a patterned line sampled along its longitudinal length, commonly quantified as three times the standard deviation ($3\sigma_{\text{LWR}}$) of measured critical dimensions. While line edge roughness (LER) measures the spatial deviation of a single isolated boundary, line width roughness captures the coupled variance of both edges ($w(y) = x_{\text{right}}(y) - x_{\text{left}}(y)$), directly governing transistor channel length variability, gate threshold voltage ($V_{\text{th}}$) dispersion, sub-threshold drain leakage ($I_{\text{off}}$), and interconnect resistance fluctuation. In sub-3nm nanosheet logic and dense memory arrays, LWR does not scale down proportionally with feature size, causing stochastic critical dimension variation to consume an increasingly severe fraction of the total error budget.
Line width roughness relates directly to single-edge roughness through the spatial cross-correlation between opposing line edges. If the position deviations of the left and right edges along coordinate $y$ are denoted $\delta x_L(y)$ and $\delta x_R(y)$, the total variance of the local feature width $w(y) = w_0 + \delta x_R(y) - \delta x_L(y)$ is derived as:
where $\rho_{LR}$ is the cross-edge correlation coefficient ($-1 \le \rho_{LR} \le 1$). Opposing edges may be correlated, uncorrelated, or anticorrelated, and that relationship can change with spatial frequency, pitch, imaging, resist, development, and etch. The familiar $\sqrt{2}$ relationship is a special case for equal edge variances with zero covariance:
Power spectral density (PSD) decomposition separates high-frequency noise from low-frequency CD bias. A single standard deviation value ($3\sigma_{\text{LWR}}$) provides an incomplete description because it fails to capture the spatial wavelength distribution of roughness. Calculating the Fourier transform of the line width autocorrelation function yields the power spectral density:
where $\text{PSD}(0)$, $\xi$, and $H$ are fitted parameters whose values depend on process, sampling, bandwidth, extraction, and model convention. Etch transfer is frequency-dependent: a process may attenuate, preserve, or add roughness in different bands, so no universal crossover guarantees smoothing or direct transfer.
LWR in transistor gate channels causes exponential amplification of off-state drain leakage current ($I_{\text{off}}$). Because sub-threshold leakage current scales exponentially with channel length ($I_{\text{off}} \propto \exp(-q V_{\text{th}} / k_B T) \propto \exp(-L_{\text{eff}} / l_{\text{char}})$), localized pinch points where line width narrows experience severe drain-induced barrier lowering (DIBL). As a result, the average leakage current across a rough gate is substantially higher than that of an ideal smooth gate of identical average CD:
where $l_{\text{char}}$ is the characteristic electrostatics scaling length of the device. The electrical penalty must be computed from the measured roughness spectrum and correlation together with the actual device geometry, electrostatics, transport, layout, and bias; a marketing node label alone cannot determine a leakage multiplier.
Metrology measurement noise de-embedding is required to obtain unbiased physical line width roughness. When automated critical-dimension scanning electron microscopes (CD-SEM) scan a feature, primary electron beam Poisson shot noise adds high-frequency white noise to the measured edge position. Reporting the raw standard deviation overestimates physical wafer roughness. Rigorous metrology fits the high-frequency floor of the experimental PSD to extract and subtract SEM noise:
| Process Platform & Node | Target Nominal CD ($w_0$) | Target $3\sigma_{\text{LWR}}$ Spec | $\sigma_{\text{LWR}} / w_0$ Ratio | Key Mitigation Strategy |
|---|---|---|---|---|
| 14nm FinFET Node (193i Immersion) | 20nm Fin Width | $\le 2.4\text{ nm}$ | ~12.0% | Self-aligned spacer patterning (SADP) to eliminate direct litho LWR |
| 7nm FinFET Node (0.33 NA EUV) | 16nm Metal Line | $\le 2.0\text{ nm}$ | ~12.5% | High-dose EUV exposure ($> 45\ \text{mJ/cm}^2$) and low-acid-diffusion CAR |
| 5nm / 3nm Nanosheet (0.33 NA EUV) | 12nm Gate Length | $\le 1.4\text{ nm}$ | ~11.7% | Post-litho directional plasma smoothing and spin-on carbon hardmasks |
| 2nm / A14 Node (0.55 High-NA EUV) | 9nm Metal Wire | $\le 1.0\text{ nm}$ | ~11.1% | Inorganic metal-oxide photoresists (MOR) and supercritical CO₂ rinse |
| Sub-1nm / 3D CFET Architecture | 7nm Nanosheet Channel | $\le 0.7\text{ nm}$ | ~10.0% | Atomic layer etching (ALE) cycle smoothing and selective epitaxy |
Post-lithography plasma smoothing and directional gas cluster ion beam (GCIB) etching mitigate high-frequency LWR. During plasma pattern transfer through the underlying bottom antireflective coating (BARC) and spin-on carbon (SOC) hardmask, pulsed hydrogen/methane or fluorocarbon chemistries preferentially sputter sharp roughness asperities. Such treatments can attenuate selected PSD bands, but improvement and accompanying CD bias, selectivity, damage, residue, and low-frequency changes must be measured on the complete transfer stack.
Ensuring nanometer-scale transistor matching requires treating line width roughness as a stochastic-photon-acid-diffusion-and-channel-leakage lens. As physical gate lengths scale toward single-digit nanometers, average critical dimension becomes an incomplete metric without full stochastic roughness characterization. Co-optimizing resist quantum efficiency, optical image log-slope, de-embedded PSD metrics, and plasma smoothing ensures that advanced logic chips deliver high operating frequencies without runaway parametric leakage.