Low Temperature Epitaxy
Low Temperature Epitaxy is the crystal growth technique that deposits epitaxial silicon, SiGe, or III-V semiconductor films at temperatures significantly below conventional epitaxy (350-550°C vs. 600-850°C) — essential for advanced CMOS process flows where the thermal budget must be minimized to prevent dopant diffusion, strain relaxation, and degradation of previously formed structures, particularly critical for gate-all-around nanosheet transistors, 3D sequential integration, and back-end-of-line compatible epitaxy.
Why Low Temperature
- Dopant diffusion: At 800°C, boron diffuses ~5nm in 30 seconds → junction broadens → Vt shift.
- Strain relaxation: High temperature allows SiGe dislocations to form → strain lost → mobility gain lost.
- Prior structures: Metal gates, silicides, contacts degrade above 500-600°C.
- 3D sequential: Top-tier devices formed above bottom-tier → must not damage lower tier → <500°C limit.
- Each new node tightens thermal budget further → drives epitaxy temperature down.
Temperature Evolution Across Nodes
| Node | Epitaxy Step | Typical Temperature | Driver |
|---|---|---|---|
| 28nm | SiGe S/D | 650-700°C | Standard |
| 14nm FinFET | SiGe S/D | 600-650°C | Dopant control |
| 7nm | SiGe S/D | 550-600°C | Strain preservation |
| 5nm | SiGe S/D + channel | 500-550°C | GAA integration |
| 3nm/2nm | GAA S/D | 450-500°C | Multi-sheet control |
| 3D sequential | Top-tier epi | 350-450°C | Bottom-tier survival |
Low-T Precursors
| Precursor | Decomposition Temp | Film | Notes |
|---|---|---|---|
| SiH₄ (silane) | ~550°C | Si | Higher-order silanes preferred |
| Si₂H₆ (disilane) | ~400°C | Si | 150°C lower than SiH₄ |
| Si₃H₈ (trisilane) | ~350°C | Si | Lowest Si precursor temperature |
| GeH₄ (germane) | ~300°C | Ge | Enables low-T SiGe |
| B₂H₆ (diborane) | ~300°C | B doping | Low-T p-type doping |
Challenges at Low Temperature
| Challenge | Cause | Impact |
|---|---|---|
| Slow growth rate | Less thermal energy for decomposition | Lower throughput |
| Poor selectivity | Nucleation on dielectrics at low T | Loss of selective growth |
| Higher impurity incorporation | Insufficient energy to desorb contaminants | Carbon, oxygen in film |
| Rougher surface morphology | Limited adatom mobility | Higher interface roughness |
| Incomplete dopant activation | Low T insufficient for activation | Higher resistance |
Mitigation Strategies
- Higher-order precursors: Si₃H₈ decomposes at 350°C vs. SiH₄ at 550°C.
- Plasma-enhanced epitaxy: Plasma provides energy → allows crystalline growth at lower temperature.
- Cyclic deposition-etch: Deposit → etch non-selective growth → re-deposit → maintains selectivity.
- UV-assisted CVD: Photon energy supplements thermal energy.
- Catalytic CVD: Metal catalyst on surface lowers decomposition barrier.
3D Sequential Integration
- Bottom tier: Full standard CMOS (transistors, contacts, first metal layers).
- Inter-tier bonding: Oxide bond at 200°C.
- Top tier: Devices formed entirely at <500°C → must not exceed this → all epi at 400-450°C.
- Low-T epi quality at 400°C: Defect density 10-100× higher than 600°C → active research area.
Low temperature epitaxy is the thermal budget frontier that determines how many 3D integration tiers are feasible and how aggressively transistor junctions can be scaled — every 50°C reduction in epitaxy temperature opens new integration possibilities (from preserving strain in nanosheet S/D to enabling monolithic 3D stacking), making low-temperature growth one of the most active and consequential research areas in semiconductor process development.