Mask

Photomask (reticle): the master pattern for a chip layer. A photomask controls where exposure light reaches the wafer. Projection optics form a smaller image in photoresist; etching or deposition transfers it into a material layer. The same master is reused across many exposure fields and wafers.

1. Clear gaps pass light; opaque regions block it. A binary DUV mask has patterned absorber on transparent fused silica. This drawing isolates the transmission principle; a real scanner forms the wafer image through diffraction and projection optics.

The wafer image is smaller. Conventional reduction scanners commonly use a 4× mask: an 80 nm mask feature corresponds geometrically to 20 nm on the wafer. Optical effects and processing change the final dimension, so this ratio alone does not guarantee printability. High-NA EUV uses different reduction factors in its two axes.

2. EUV needs a patterned mirror. At 13.5 nm, ordinary transparent optics absorb too much light. An EUV reticle carries an absorber pattern over a protective cap and a molybdenum/silicon multilayer reflector. The exposed mirror regions return light toward the projection optics. A low-expansion substrate supports the stack.

The stack affects the image. EUV illumination arrives at an angle, so absorber height can cause shadowing and orientation-dependent imaging. Buried multilayer defects can distort the reflected wavefront. Inspection must assess the resulting wafer image, including phase effects.

3. A defect on the master repeats. A printable reticle flaw can recur at the same position in every exposed field, across many wafers. A random wafer particle usually causes localized damage. An exposure field may contain one die or several dies; the repeating unit is the field.

4. Correct the design before writing the mask. Diffraction rounds corners and changes line ends. Optical proximity correction (OPC) adjusts mask edges and adds assist features. Inverse lithography (ILT) can generate more complex contours. Both aim to print the intended wafer shape over an acceptable range of focus and exposure dose.

An electron-beam writer exposes resist on the blank. Development and etching form the absorber pattern, followed by cleaning. Measurements check feature width and placement. Defect review determines whether a flaw will print; repair is followed by another qualification check.

Phase and particles matter too. Phase-shift DUV masks control both transmission and phase to improve image contrast. A pellicle holds contamination away from the mask's image plane, making particles less likely to print sharply. EUV pellicles also face demanding transmission and heating requirements. Inspection and careful handling remain essential.

A mask set is reused through production. A chip requires many patterned layers and therefore many reticles; multipatterning can require several reticles for one design layer. Data preparation, writing, inspection, repair and qualification contribute to cost and lead time. Repeated cleaning and exposure can alter mask condition, so fabs track usage and recurring wafer defects.

The practical takeaway: qualify the image the wafer receives. A useful reticle must deliver the right dimensions, placement and defect performance throughout its production life.

Further reading: ZEISS, Mask Qualification; ASML, The EUV Pellicle.