Mask Rule Check

Mask rule check (MRC) verifies that OPC- and ILT-corrected mask patterns are actually manufacturable by the mask shop before they're ever sent to a writer — checking minimum feature size, minimum spacing, maximum jog width, and corner-rounding limits against the real physical constraints the mask writer and mask etch process impose. It's the step that catches patterns which look perfect in simulation but simply cannot be built on real mask-making equipment, before that gap becomes an expensive, physical mistake.

MRC: Can the Mask Shop Actually Build This? A pattern that looks perfect in OPC simulation can still be physically impossible to write and etch. WHAT GETS CHECKED min. space jog width limit min. corner radius THE FEEDBACK LOOP OPC / ILT run MRC check violation found re-run with tighter constraint loop exits only once MRC-clean WHY SKIPPING MRC IS SO EXPENSIVE A violation that reaches the mask writer doesn't fail gracefully — it produces a real, physical mask with a genuine CD defect, discovered only at inspection or, worse, only after wafers printed from it come back bad. Rework at that stage costs vastly more than catching the same violation in a software check beforehand. Minimum feature size on mask is typically 40-60 nanometers — roughly 10-15 nanometers once 4x wafer reduction applies. MRC is the software gate that stands between a simulated correction and a physically committed mask.

Minimum feature size and minimum spacing rules exist because a mask writer, regardless of which technology actually exposes the pattern, has a genuine physical resolution floor it can't write below. OPC and inverse lithography optimization can mathematically propose features finer than that floor if left unconstrained, because the simulation itself has no inherent awareness of what a real mask writer can or can't physically expose. MRC enforces these limits directly — typically requiring mask features above roughly 40 to 60 nanometers, which translates to roughly 10 to 15 nanometers once a scanner's 4x reduction optics project the pattern onto the wafer — catching any OPC-proposed feature that's crossed below what the chosen writer and etch process can actually deliver.

Maximum jog width constraints address a different physical reality: a mask writer and the subsequent etch process both handle smoothly-varying edges far more reliably than sharp, frequent steps in an edge's position. A "jog" is a small step where a feature's edge position shifts abruptly rather than running smoothly, and OPC corrections sometimes introduce exactly this kind of stepped edge while trying to compensate for diffraction effects. If those jogs are too narrow for the mask writer to resolve cleanly, or too fine for the etch process to transfer faithfully, the finished mask edge ends up looking nothing like the intended, carefully-corrected shape — which defeats the entire purpose of the OPC correction that created the jog in the first place.

Corner rounding limits exist because every mask writer, regardless of technology, physically rounds sharp corners to some minimum radius during exposure — a real, unavoidable physical effect rather than a simulation artifact to be eliminated. A perfectly sharp 90-degree corner simply isn't achievable with any real writing technology; corners always round off to some finite radius set by the writer's resolution and the resist's own response to exposure. MRC defines the minimum corner radius the chosen process can actually achieve and flags any OPC-generated feature whose design assumes a sharper corner than that — catching a mismatch between what the simulation assumed and what the physical writing process will actually deliver.

The MRC-to-OPC feedback loop is iterative by design, because a correction tightened to fix one violation can easily introduce a different one elsewhere, requiring the whole cycle to repeat until every rule genuinely passes simultaneously. OPC and inverse lithography re-run with tighter constraints after an MRC violation is flagged, but the adjusted correction then needs to be checked against every MRC rule again, not just the one that originally failed — a correction that fixes a spacing violation might inadvertently create a jog-width violation somewhere nearby. This loop only terminates once a pattern passes every single MRC rule simultaneously, which is why MRC-clean is treated as a hard, non-negotiable gate rather than a goal to approximate.

The economic case for catching MRC violations before writing, rather than discovering them afterward, is stark precisely because of where in the mask-making flow each discovery point sits. A violation caught in software, before any physical mask has been touched, costs essentially nothing beyond the computation time to re-run OPC. The same violation, if it reaches the mask writer undetected, produces a real, physically defective mask — caught at best during mask inspection (requiring expensive repair or scrapping that specific mask), and at worst only after production wafers printed from that defective mask come back showing a systematic CD error traced back to the mask itself. This cost asymmetry is exactly why MRC runs as a mandatory, automated gate rather than an optional sanity check.

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